Patents by Inventor Howard Thomas Olnowich

Howard Thomas Olnowich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6823429
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6408341
    Abstract: A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: June 18, 2002
    Assignee: International Business Machines Corporation
    Inventors: James William Feeney, Howard Thomas Olnowich, George William Wilhelm, Jr.
  • Patent number: 6389476
    Abstract: A network adapter capable of adapting its transmission speed to that of another adapter of the same or slower speed so as to mix adapters of different speeds in the same communication network. In send mode, the adapter selects one of a plurality of transmission speeds based on the message header including a field specifying the message speed, which speed is known to be supported by the adapter at the addressed receive node. The sending adapter prefixes the message with a synchronization byte which defines transmission speed selected and transmits the message at the selected speed. In receive mode, the adapter decodes within one clock cycle the message speed from the message synchronization byte, and responsive thereto generates the clock for gating the receive message into adapter memory.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: May 14, 2002
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6343346
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: January 29, 2002
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6263374
    Abstract: An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: July 17, 2001
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Michael Wayland Dotson, James William Feeney, Michael Hans Fisher, John David Jabusch, Robert Francis Lusch, Michael Anthony Maniguet
  • Patent number: 6243378
    Abstract: Contention losses are minimized in path searching, circuit-switched networks by adding intelligence to the last stage of the network. A count of number of bytes remaining to be transferred in each active message is maintained in real time for each output port of the network. If contention arises at the last stage switch being requested in camp-on mode to make a connection to a busy output port, the switch checks the bytes remaining count and responds differently depending on how the bytes remaining count compares to a preset threshold register. If the count remaining is below the threshold, the last stage switch accepts the camp-on request, because the desired output port will be available shortly. If the count remaining is above the threshold or below the threshold but another user is camped-on, the switch rejects the camp-on request to the last stage, because the desired output port will not be available shortly. In this case further path searching would be meaningless.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6226683
    Abstract: Disclosed is is a switch-based network interconnection which uses intelligent switching apparatus devices for improving the performance and connection establishing capability of multi-stage switching networks. The invention method is particularly effective In asynchronous circuit-switched networks. The most important feature of the invention methodology is the an increasing probability for the success of making a connection through all the stages of a multi-satge network. As a connection progresses through a multi-stage network, it must win successive stages of the network, one at a time, until it has made its way from on side of the network to the other and established the commanded source-to-destination connection. The uniqueness in the present invention is that as the connection at each stage of the network is established, looking forward to the next stage, the probability will be greater of establishing the next connection without encountering blocking than it was for the present stage.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: May 1, 2001
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Jehoshua Bruck, James William Feeney, Eli Upfal
  • Patent number: 6215412
    Abstract: A new asynchronous approach used to quickly and dynamically switch input port connections to output port connections and to resolve contention. The switch is self-routing in two cycle times at the same high speed serial rate that data is transferred through the switch. The normal mode of the switch requires absolutely no synchronization amongst any of the input and output ports which interface to the switch. The switch is void of centrally controlled clocking and any data buffering. Data traverses the switch only encountering three gate delays—on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip, and yet the logic implementation is extremely simple and low in gate count, so the switch design is never gate limited. The protocol requires several parallel data lines plus two or three control lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Peter Anthony Franaszek, Christos John Georgiou, Robert Francis Lusch, Joseph Michael Mosley, Howard Thomas Olnowich
  • Patent number: 6122659
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: September 19, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6122674
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: September 19, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6098123
    Abstract: A dynamic allocation system and method is provided for allocating memory bandwidth associated with a store and forward memory communicating between a node processsor and a network. Dynamic allocation is controlled by a state machine in a network adapter, which monitors on a real time basis the active users of the network adapter memory, the node processor writing or reading adapter memory, the network sending port, and the network receiving port. Bandwidths are allocated to users with instant response to user bandwidth demand changes. Programmable options allow a node processor to control bandwidth allocations for various user scenarios.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: August 1, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6092155
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: July 18, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6072781
    Abstract: A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: June 6, 2000
    Assignee: International Business Machines Corporation
    Inventors: James William Feeney, Howard Thomas Olnowich, George William Wilhelm, Jr.
  • Patent number: 6047113
    Abstract: A network adapter capable of adapting its transmission speed to that of another adapter of the same or slower speed so as to mix adapters of different speeds in the same communication network. In send mode, the adapter selects one of a plurality of transmission speeds based on the message header including a field specifying the message speed, which speed is known to be supported by the adapter at the addressed receive node. The sending adapter prefixes the message with a synchronization byte which defines transmission speed selected and transmits the message at the selected speed. In receive mode, the adapter decodes within one clock cycle the message speed from the message synchronization byte, and responsive thereto generates the clock for gating the receive message into adapter memory.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: April 4, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6044438
    Abstract: A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: March 28, 2000
    Assignee: International Business Machiness Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6044059
    Abstract: Contention losses are minimized in path searching, circuit-switched networks by adding intelligence to the last stage of the network. A count of number of bytes remaining to be transferred in each active message is maintained in real time for each output port of the network. If contention arises at the last stage switch being requested in camp-on mode to make a connection to a busy output port, the switch checks the bytes remaining count and responds differently depending on how the bytes remaining count compares to a preset threshold register. If the count remaining is below the threshold, the last stage switch accepts the camp-on request, because the desired output port will be available shortly. If the count remaining is above the threshold or below the threshold but another user is camped-on, the switch rejects the camp-on request to the last stage, because the desired output port will not be available shortly. In this case further path searching would be meaningless.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: March 28, 2000
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 6034956
    Abstract: The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: March 7, 2000
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Jehoshua Bruck, Michael Hans Fisher, Joel Mark Gould, John David Jabusch, Arthur Robert Williams
  • Patent number: 5933428
    Abstract: An adapter with two or more tails for interconnecting a node to a multi-stage interconnection network. The plurality of tails create various options. Option 1 connects a 2-tailed adapter to two sub-networks comprising the same network to provide cost effective non-blocking networks. Both serial and parallel searches through the sub-networks for non-blocked paths are supported. Option 2 connects the 2-tailed adapter to redundant networks to provide fault tolerance in case of the failure of one network. Option 3 forms direct connections amongst two or three nodes without requiring a central switch. Instead, each tail provides a direct link to a different node. Option 4 extends the adapter to provide additional tails; 3-tailed adapters provide direct links amongst four nodes, 4-tailed adapters provide direct links amongst five nodes, etc. Option 5 interconnects similar multi-tailed adapters to provide ring or hyper-cube networks without requiring a central switch.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: August 3, 1999
    Assignee: International Business Machines Corporation
    Inventor: Howard Thomas Olnowich
  • Patent number: 5922063
    Abstract: A method and apparatus for reducing the software overhead of message passing in parallel systems. Special purpose hardware assists in constructing each data message sent through a network. Message passing systems generally require that every message be prefixed with a message header describing the key control parameters of the message. The software task is to construct the message header for every message individually and to transmit the header prefixed to every message. The software is relieved of constructing the message header and uses special purpose hardware to accomplish the job more efficiently.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: July 13, 1999
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Michael Wayland Dotson, James William Feeney, Robert Francis Lusch, Michael Anthony Maniguet
  • Patent number: 5920704
    Abstract: An asynchronous switching apparatus is enabled to reshape data pulses and eliminate skewing problems as data is transmitted through the switch. The switching apparatus still functions asynchronously and maintains all the advantages of asynchronous operation, such as, not requiring the alignment and distribution of a central clock, having no central point failure mechanisms, and allowing each node of the parallel system to function free of synchronization requirements with other nodes.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: July 6, 1999
    Assignee: International Business Machines Corporation
    Inventors: Howard Thomas Olnowich, Donald George Grice, Arthur Robert Williams