Abstract: The present invention relates to the manufacture of substrates for semiconductor device manufacturing particularly for applications that involved wafer-to-wafer bonding for SOI or MEMS structures. Although previous techniques have been applicable to single crystal wafers using bonding and annealing, the current techniques offer the unique capability of utilizing lower cost semiconductor materials, even when they contain dislocations or other growth associated stress fields; such as poly or multi-crystalline silicon and seed, or tail ends of CZ or FZ grown ingots. This invention provides a means of obtaining superior global and local flatness, along with nanoscale roughness variations across the surfaces so that cost and throughput are optimized.

Abstract: According to the invention, a method for preparing multicrystalline substrates as “handle wafers” for subsequent bonding to “device layer” quality materials is disclosed. In one step, starting with a suitable substrate such as multicrystalline silicon, the substrate surface is prepared for layer transfers by using a novel CMP method in which, after a suitable period of polishing at elevated pH, a surfactant and rinse material is gradually introduced into the slurry to lower pH and remove wear materials from the slurry. In another step, a filler layer of polycrystalline silicon is transferred to the face of the polished substrate to a predetermined thickness, thus filling in surface defects remaining after the initial CMP step, and a subsequent CMP polishing step is performed. By these steps, multicrystalline substrates can be prepared with surface roughness of twenty Angstroms or less, which is suitable for defect-free bonding to device-layer materials in this embodiment.