Abstract: A circuit having a single branch, which is controllable to implement either a left or right shift of bits of a data word. Preferably, the circuit is controllable to implement any selected one of the following operations: a left or right shift of bits of the word; and rotation (to the left or right) of bits of the word. In a preferred implementation, the circuit includes a set of multiplexer stages and circuitry for selectively inverting the order of the bits of the word input to, and the word output from, the set of multiplexer stages. Each of the multiplexer stages shifts the bits of the word it receives either by zero bits (in response to a first control signal), or by a positive number of bits (in response to a second control signal). By selectively controlling various subsets of the multiplexer stages, the bits of the input word can be shifted by any of a number of places (from zero to N, where N is some positive number).