Patents by Inventor Howard W. Patterson

Howard W. Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Temperature compensated on-chip bias circuit for linear RF HBT power amplifiers
    Patent number: 7057462
    Abstract: An RF amplifier is disclosed having a first and second current mirror module. The first and second current mirror modules each provide current to affect the quiescent bias current of the RF amplifier.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 6, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Li-Hung Kang, Howard W. Patterson, Zhongian Yuan
  • Integrated circuit having passive circuit elements
    Patent number: 5481131
    Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: January 2, 1996
    Assignee: Motorola, Inc.
    Inventors: Joseph Staudinger, Warren L. Seely, Howard W. Patterson
  • Integrated circuit having passive circuit elements
    Patent number: 5416356
    Abstract: An integrated circuit is formed from a first layer of conductive material (30) which is separated from a second layer of conductive material (39) by a layer of dielectric material (36). The first layer of conductive material (30) is patterned to form a first plate (32, 59) of a capacitor (22, 50, 62, 72). An electrical interconnect (33, 63) is formed within the first plate (32, 59), respectively. A via (37) is formed in the layer of dielectric material (36). A second layer of conductive material (39) is patterned to form a second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72) and a planar spiral inductor (21, 51, 61, 71). The planar spiral inductor (21, 51, 61, 71) is surrounded by the second plate (42, 56, 66, 76) of the capacitor (22, 50, 62, 72).
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: May 16, 1995
    Assignee: Motorola, Inc.
    Inventors: Joseph Staudinger, Warren L. Seely, Howard W. Patterson