Abstract: Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.

Abstract: Systems and methods for the synchronization and display of video input signals. The input signals, associated with input channels, are received by a controller. On a frame-by-frame basis, the controller controls the writing of the input signals to, and the reading of the input signals from, a memory. A frame rate control module controls frame-level synchronization between the writing operations and reading operations of the controller so that when a frame is written to the memory is not simultaneously read from the memory. The controller writes video frames for each input channel to, and reads video frames for each input channel from, the memory on a channel-by-channel basis such that the video frames corresponding to each input channel are read and written independently of one another. This allows the input signals to be unsynchronized with one another without harming the writing operations, reading operations, and display of the input signals.

Abstract: A video system including a plurality of video sources, a recording device, a memory, and a controller. The controller receives video frames from the video sources and includes a first and a second write control module, a read control module, and a frame rate control module. The first write control module includes a write pointer and writes a first video frame to a first frame buffer. The second write control module includes a second write pointer and writes a second video frame to a second frame buffer. The read control module includes a read pointer. The frame rate control module controls the reading of the first and second video frames based on a multiplexing order and a read memory location of the read pointer respecting a write memory location of the write pointer. The read control module outputs a multiplexed signal to the recording device according to the multiplexing order.

Abstract: A multi-processor system comprises a clock generator, a clock controller, a main processor, a plurality of co-processors and an interrupt control interface. Because the main processor and the co-processors need not work together to deliver the processing result, the multi-processor system may be designed that each processor in the multi-processor system is independently switched to operate at lower clock or power down completely according to the feedback of the hardware performance detection for each processor when the whole system is in active usage. This means on-demand power saving for the multi-processor system, so as to save power greatly.

Abstract: In one embodiment of the present invention, a processing system for processing information efficiently and cost-effectively by switching between execution of time-critical and non-time-critical tasks includes a processing unit. The processing system further includes a first register group coupled to the processing unit and including a first set of registers, the processing unit reading the status of the first set of registers to execute time-critical tasks.