Patents by Inventor Hoyoung C. Choe

Hoyoung C. Choe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STRESS REDUCTION INTERPOSER FOR CERAMIC NO-LEAD SURFACE MOUNT ELECTRONIC DEVICE
    Publication number: 20170150596
    Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Inventors: Tse E. Wong, Shea Chen, Hoyoung C. Choe
  • Stress reduction interposer for ceramic no-lead surface mount electronic device
    Patent number: 9648729
    Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 9, 2017
    Assignee: RAYTHEON COMPANY
    Inventors: Tse E. Wong, Shea Chen, Hoyoung C. Choe
  • Digital beam stabilization techniques for wide-bandwidth electronically scanned antennas
    Patent number: 6693589
    Abstract: Techniques for maintaining beam pointing for an Electronically Scanned Antenna (ESA) as its frequency is varied over a wide frequency bandwidth. A technique uses discrete phase shifters, a number of stored states, and a control methodology for rapidly switching among the states.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: February 17, 2004
    Assignee: Raytheon Company
    Inventors: Eric N. Boe, Robert E. Shuman, Richard D. Young, Hoyoung C. Choe, Adam C. Von
  • Digital beam stabilization techniques for wide-bandwidth electronically scanned antennas
    Publication number: 20030142015
    Abstract: Techniques for maintaining beam pointing for an Electronically Scanned Antenna (ESA) as its frequency is varied over a wide frequency bandwidth. A technique uses discrete phase shifters, a number of stored states, and a control methodology for rapidly switching among the states.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventors: Eric N. Boe, Robert E. Shuman, Richard D. Young, Hoyoung C. Choe, Adam C. Von