Patents by Inventor Ho-Yung David Hwang
Ho-Yung David Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869807Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.Type: GrantFiled: June 1, 2021Date of Patent: January 9, 2024Assignee: Applied Materials, Inc.Inventors: Lili Feng, Yuqiong Dai, Madhur Sachan, Regina Freed, Ho-yung David Hwang
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Publication number: 20230384680Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.Type: ApplicationFiled: August 4, 2023Publication date: November 30, 2023Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
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Publication number: 20230215735Abstract: A method of forming features over a semiconductor substrate is provided. The method includes supplying a gas mixture over a surface of a substrate at a continuous flow rate. A first radio frequency (RF) signal is delivered to an electrode while the gas mixture is supplied at the continuous flow rate to deposit a polymer layer over the surface of the substrate. The surface of the substrate includes an oxide containing portion and a nitride containing portion. A second RF signal is delivered to the electrode while continuously supplying the gas mixture at the continuous flow rate to selectively etch the oxide containing portion relative to the nitride containing portion.Type: ApplicationFiled: November 14, 2022Publication date: July 6, 2023Inventors: Lei LIAO, Yung-chen LIN, Chi-I LANG, Ho-yung David HWANG
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Patent number: 11638374Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: GrantFiled: April 14, 2022Date of Patent: April 25, 2023Assignee: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Publication number: 20230045689Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: ApplicationFiled: October 18, 2022Publication date: February 9, 2023Applicant: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Patent number: 11508618Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.Type: GrantFiled: July 14, 2021Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang
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Patent number: 11508617Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.Type: GrantFiled: October 24, 2019Date of Patent: November 22, 2022Assignee: Applied Materials, Inc.Inventors: Hao Jiang, Chi Lu, He Ren, Chi-I Lang, Ho-yung David Hwang, Mehul Naik
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Publication number: 20220367186Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: Applied Materials, Inc.Inventors: Nancy Fung, Chi-I Lang, Ho-yung David Hwang
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Publication number: 20220359289Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Patent number: 11437238Abstract: Methods and film stacks for extreme ultraviolet (EUV) lithography are described. The film stack comprises a substrate with a hard mask, bottom layer, middle layer and photoresist. Etching of the photoresist is highly selective to the middle layer and a modification of the middle layer allows for a highly selective etch relative to the bottom layer.Type: GrantFiled: July 8, 2019Date of Patent: September 6, 2022Assignee: Applied Materials, Inc.Inventors: Nancy Fung, Chi-I Lang, Ho-yung David Hwang
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Patent number: 11437274Abstract: Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.Type: GrantFiled: September 14, 2020Date of Patent: September 6, 2022Assignee: Micromaterials LLCInventors: Regina Freed, Madhur Sachan, Susmit Singha Roy, Gabriela Alva, Ho-yung David Hwang, Uday Mitra, El Mehdi Bazizi, Angada Bangalore Sachid, He Ren, Sushant Mittal
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Publication number: 20220238531Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: ApplicationFiled: April 14, 2022Publication date: July 28, 2022Applicant: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-Yung David Hwang, Samuel E. Gottheim
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Publication number: 20220199401Abstract: Methods for depositing boron-containing films on a substrate are described. The substrate is exposed to a boron precursor and a plasma to form the boron-containing film (e.g., elemental boron, boron oxide, boron carbide, boron silicide, boron nitride). The exposures can be sequential or simultaneous. The boron-containing films are selectively deposited on one material (e.g., SiN or Si) rather than on another material (e.g., silicon oxide).Type: ApplicationFiled: December 13, 2021Publication date: June 23, 2022Applicant: Applied Materials, Inc.Inventors: Yung-Chen Lin, Chi-I Lang, Ho-yung David Hwang
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Patent number: 11335690Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: GrantFiled: January 12, 2021Date of Patent: May 17, 2022Assignee: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Publication number: 20220074668Abstract: A controller includes a non-transitory computer readable medium configured to store information related to a target temperature of a wafer, a target temperature of a heating element, a temperature of the wafer, and a temperature of the heating element. The controller further includes a processor connected to the non-transitory computer readable medium, the processor configured to generate at least one heating signal during a baking process to adjust a duration of an entirety of the baking process in response to the temperature of the wafer and the temperature of the heating element.Type: ApplicationFiled: November 16, 2021Publication date: March 10, 2022Inventors: Tzung-Chen WU, Heng-Jen LEE, Ho-Yung David HWANG, Wen-Zhan ZHOU
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Publication number: 20220013624Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: ApplicationFiled: September 28, 2021Publication date: January 13, 2022Applicant: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu
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Patent number: 11204200Abstract: A method includes supporting a wafer on a heating element, wherein the heating element is located in a baking chamber. The method further includes heating the wafer for a first duration using the heating element. The method further includes measuring a temperature of the heating element and a temperature of the wafer during the first duration to obtain temperature information. The method further includes adjusting an amount of heat provided by the heating element during the first duration, wherein the adjusting of the amount of heat includes decreasing the amount of heat provided by the heating element as a rate of change of the temperature information versus time increases.Type: GrantFiled: June 25, 2018Date of Patent: December 21, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzung-Chen Wu, Wen-Zhan Zhou, Heng-Jen Lee, Ho-Yung David Hwang
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Publication number: 20210391215Abstract: Apparatuses and methods to provide fully self-aligned first metallization lines, M1, via, and second metallization lines, M2, are described. A first metallization line comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate; a second metallization line comprising a set of second conductive lines on an etch stop layer above the first metallization line, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and at least one via between the first metallization line and the second metallization line, the at least one via comprising a via metallization layer, wherein the at least one via is self-aligned along the second direction to one of the first metallization lines and the at least one via is self-aligned along the first direction to one of the second metallization lines, the second direction crossing the first direction at an angle.Type: ApplicationFiled: June 1, 2021Publication date: December 16, 2021Applicant: Applied Materials, Inc.Inventors: Lili Feng, Yuqiong Dai, Madhur Sachan, Regina Freed, Ho-yung David Hwang
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Publication number: 20210343592Abstract: Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Applicant: Applied Materials, Inc.Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang
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Patent number: 11164938Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments relate to the formation of self-aligned DRAM capacitors. More particularly, certain embodiments relate to the formation of self-aligned DRAM capacitors utilizing the formation of self-aligned growth pillars. The pillars lead to greater capacitor heights, increase critical dimension uniformity, and self-aligned bottom and top contacts.Type: GrantFiled: March 23, 2020Date of Patent: November 2, 2021Assignee: Micromaterials LLCInventors: Uday Mitra, Regina Freed, Ho-yung David Hwang, Sanjay Natarajan, Lequn Liu