Abstract: A rational number operation unit comprising division means which receives a rational number having numerator and denominator to be reduced for sequentially determining terms d.sub.1, d.sub.2, . . . of a continued fraction for the rational number ##STR1## or data S.sub.1, S.sub.2, . . . , the division means carrying out a first division for the numerator as a dividend and the denominator as a divisor, producing a quotient thereof as the first term d.sub.1 or the dependent data S.sub.1, carrying out a second division for a residue thereof as a new divisor and the divisor in the first division as a new dividend, producing a quotient thereof as the second term d.sub.2 or depending data S.sub.2, . . . , carrying out an (i+1)th division for a residue of the i-th division as a new divisor and the divisor in the i-th division as a new dividend, producing a quotient thereof as the term d.sub.i+1 or depending data S.sub.i+1, calculation means responsive to the term d.sub.i or depending data S.sub.i for calculatingP.

Abstract: An operation unit has a significant digit number judging circuit in which to detect as to whether or not a significant digit number of exponent part variable length data obtained as an arithmetic result becomes smaller than a specified minimum significant digit number, this operation unit manipulating data characterized in that exponent and mantissa parts thereof vary in length according to data values and its data length is fixed. In a first embodiment, there is a circuit for detecting the significant digit number of the resultant data with a variable length exponent part, the data being gained by a step wherein exponent and mantissa data are combined by using the exponent data of the resultant fixed length exponent and mantissa data.

Abstract: A floating-point data processing apparatus operates to generate exponent data of fixed length from floating-point data composed of (a) a sign bit indicating a mantissa sign, (b) a first exponent part which has bit length determined in dependence upon a significant bit length necessary for binary expression of an exponent and which has all its bits determined at 1 or 0 in dependence upon the mantissa sign and the sign of said exponent, (c) a second exponent part which has its bit length determined in dependence upon the bit length of the first exponent part, which has a predetermined relationship determined in dependence upon the sign of the exponent and the mantissa sign with the significant bit part when the exponent is expressed in binary form, and the leading bit of which has a value different from the value of one bit of said first exponent part, and (d) a mantisa part which has a plurality of bits having a bit length determined in dependence upon the value of the exponent.

Abstract: An execution processing device for executing variable length floating-point data of exponent part designated by two or more kinds of representation systems and fixed length floating-point data of exponent part designated by two or more kinds of representation systems, includes a converting circuit which converts the data of various representation systems into a common representation system which is capable of expressing the data in a common data form responsive to an operation mode that is provided to discriminate the various representation systems at the time of reading and operating on the data of the various representation systems stored in a storage unit according to the same load instruction. An arithmetic unit introduces the data converted by said converting circuit into the common representation system, which performs the operation designated by the same instruction, and which produces the operation result as the data of the common representation system.

Abstract: A floating-point number operating unit utilizes a floating-point representation comprising a variable exponent part and a variable mantissa part and having a fixed length as a whole. The exponent part comprises a first bit string having the value corresponding to the exponent and a bit string comprising 1s or 0s having the length depending on the length of the first bit string; the latter bit string comprises 1s or 0s depending on a combination of the sign of the numerical value and the sign of the exponent. Moreover, the mantissa part has the length obtained by subtracting the length (one bit) of the sign bit and that of the exponent part from the fixed length.