Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: A device is configured to detect a zero voltage switching (ZVS) circuit output that includes a hard switching signal. The hard switching signal includes a false signal and a spike signal. Thereafter, the device generates digital pulse signals that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal, and uses the digital pulse signal that corresponds to the spike signal for adjusting a timing of a pulse width modulation (PWM) switching cycle.

Abstract: A device [200] is configured to detect a zero voltage switching (ZVS) circuit [110] output that includes a hard switching signal. The hard switching signal [114] includes a false signal [116] and a spike signal [118]. Thereafter, the device generates digital pulse signals [312/314] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312], and uses the digital pulse signal [314] that corresponds to the spike signal for adjusting a timing [132] of a pulse width modulation (PWM) switching cycle [Vgs ].

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.

Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.

Abstract: One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.

Abstract: A device [200, para. 24] is configured to detect a zero voltage switching (ZVS) circuit [110, para. 14] output that includes a hard switching signal. The hard switching signal [114, para. 16] includes a false signal [116, para. 16] and a spike signal [118, para. 16]. Thereafter, the device generates digital pulse signals [312/314, para. 39] that correspond to the false signal and the spike signal. Accordingly, the device filters the generated digital pulse signal that corresponds to the false signal [312, para. 41], and uses the digital pulse signal [314, para. 42] that corresponds to the spike signal for adjusting a timing [132, para. 20] of a pulse width modulation (PWM) switching cycle [Vgs 106, para. 32].

Abstract: One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.

Abstract: One example includes an interleaved resonant converter circuit. The circuit includes a plurality of resonant converter circuits that are each coupled to an output node and are configured to collectively generate an output voltage on the output node in response to a respective plurality of sets of switching signals at each of a respective plurality of phases. The circuit also includes a switching controller configured to generate each of the plurality of sets of switching signals having a variable duty-cycle relative to each other at each of the plurality of phases.

Abstract: An apparatus and a method for selective and adaptive slope compensation in peak current mode controlled power converter are disclosed. The selective and adaptive slope compensation in peak current mode controlled power converter is implemented by hardware, software, and/or combination of both to carry out start of a pulse width modulated period and delay of a start of slope compensation by a first time from the starting of the pulse width modulated period.

Abstract: A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC.

Abstract: An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak current mode controlled power converter system using selective noise blanking is implemented by hardware, software and/or combination of both to carry out adjusting a blanking time and a blanking time period to prevent change of an output of a pulse modulated waveform generator starting at the blanking time for the blanking time period.

Abstract: An apparatus and a method for selective and adaptive slope compensation in peak current mode controlled power converter are disclosed. The selective and adaptive slope compensation in peak current mode controlled power converter is implemented by hardware, software, and/or combination of both to carry out start of a pulse width modulated period and delay of a start of slope compensation by a first time from the starting of the pulse width modulated period.

Abstract: An apparatus and a method to control peak current mode controlled power converter system using selective noise blanking are disclosed. The control of the peak current mode controlled power converter system using selective noise blanking is implemented by hardware, software and/or combination of both to carry out adjusting a blanking time and a blanking time period to prevent change of an output of a pulse modulated waveform generator starting at the blanking time for the blanking time period.

Abstract: An apparatus and a method for a programmable timing in digital integrated circuits implementing peak current mode controlled power converters are disclosed. The programmable dead-time is implemented by means implemented in hardware, software, and combination of hardware and software, carrying out setting a second timer value; setting a third timer value with respect to the second timer value; detecting a reset event; reloading a second counter from a current timer value to the second timer value upon detecting the reset event; resetting a second pulse width modulated waveform amplitude from a second amplitude value to a first amplitude value upon detecting the reset event; and setting a first pulse width modulated waveform from a first amplitude value to a second value upon the second counter reaching a third value.

Abstract: A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC.