Patents by Inventor Hsi-Chang Hsu

Hsi-Chang Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220181225
    Abstract: An electronic package and a method for manufacturing the electronic package are provided. The method includes forming a slope surface on at least one side surface of at least one of a plurality of electronic components, and then disposing the plurality of electronic components on a carrier structure, such that the two adjacent electronic components form a space by the slope surface. Afterwards, an encapsulation layer is formed on the carrier structure and filled into the space to cover the two adjacent electronic components so as to disperse stress on the electronic components through the design of the space to prevent cracking due to stress concentration.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 9, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Chang-Fu Lin, Don-Son Jiang
  • Publication number: 20220173052
    Abstract: An electronic package is provided and includes at least one protective structure positioned between a first electronic element and a second electronic element on a carrier for reducing stresses generated inside the first electronic element and the second electronic element when a filling material is formed on the carrier, encapsulates the protective structure and comes into contact with the first electronic element and the second electronic element, thereby preventing cracking of the first electronic element and the second electronic element and improving the reliability of the electronic package.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 2, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsun Hsu, Chi-Jen Chen, Hsi-Chang Hsu, Yuan-Hung Hsu, Rui-Feng Tai, Don-Son Jiang
  • Publication number: 20210104465
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Application
    Filed: December 17, 2020
    Publication date: April 8, 2021
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Patent number: 10903167
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20200203277
    Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.
    Type: Application
    Filed: February 26, 2019
    Publication date: June 25, 2020
    Inventors: Jun-Chang Ding, Hong-Da Chang, Hsi-Chang Hsu
  • Publication number: 20190109092
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 11, 2019
    Inventors: Rui-Feng Tai, Hsiao-Chun Huang, Chun-Hung Lu, Hsi-Chang Hsu, Shih-Ching Chen
  • Patent number: 9607974
    Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
  • Patent number: 9397081
    Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: July 19, 2016
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
  • Publication number: 20160141227
    Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
  • Publication number: 20160141281
    Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.
    Type: Application
    Filed: October 2, 2015
    Publication date: May 19, 2016
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
  • Publication number: 20160005695
    Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a base portion having at least an electronic element embedded therein and at least a positioning unit formed around a periphery of the electronic element, wherein the positioning unit protrudes from or is flush with a surface of the base portion; and forming at least a circuit layer on the surface of the base portion and the electronic element. The circuit layer is aligned and connected to the electronic element through the positioning unit.
    Type: Application
    Filed: August 28, 2014
    Publication date: January 7, 2016
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Rui-Feng Tai, Hsiao-Chun Huang, Chun-Hung Lu, Hsi-Chang Hsu, Shih-Ching Chen
  • Patent number: 9177859
    Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: November 3, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
  • Patent number: 9040361
    Abstract: A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: May 26, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Chien-Ping Huang, Chun-Chi Ke, Hsin-Yi Liao, Hsi-Chang Hsu
  • Publication number: 20140332976
    Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.
    Type: Application
    Filed: August 29, 2013
    Publication date: November 13, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
  • Patent number: 8828796
    Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Yuan Chi, Wei-Yu Chen, Hung-Wen Liu, Yan-Heng Chen, Hsi-Chang Hsu
  • Publication number: 20140183721
    Abstract: A fabrication method of a semiconductor package is provided, which includes the steps of: providing a carrier having an adhesive layer and at least a semiconductor element having a protection layer; disposing the semiconductor element on the adhesive layer of the carrier through the protection layer; forming an encapsulant on the adhesive layer of the carrier for encapsulating the semiconductor element; removing the carrier and the adhesive layer to expose the protection layer from the encapsulant; and removing the protection layer to expose the semiconductor element from the encapsulant. Since the semiconductor element is protected by the protection layer against damage during the process of removing the adhesive layer, the product yield is improved.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 3, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yan-Heng Chen, Chiang-Cheng Chang, Jung-Pang Huang, Hsi-Chang Hsu, Yan-Yi Liao
  • Patent number: 8766456
    Abstract: A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: July 1, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hsi-Chang Hsu, Hsin-Hung Chou, Hung-Wen Liu, Hsin-Yi Liao, Chiang-Cheng Chang
  • Publication number: 20140134797
    Abstract: A method for fabricating a semiconductor package is disclosed, which includes the steps of: providing a carrier having a release layer and an adhesive layer sequentially formed thereon; disposing a plurality of semiconductor chips on the adhesive layer; forming an encapsulant on the adhesive layer for encapsulating the semiconductor chips; disposing a substrate on the encapsulant; exposing the release layer to light through the carrier so as to remove the release layer and the carrier; and then removing the adhesive layer, thereby effectively preventing the semiconductor chips from being exposed to light so as to avoid any photo damage to the semiconductor chips.
    Type: Application
    Filed: August 29, 2013
    Publication date: May 15, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chieh-Yuan Chi, Jung-Pang Huang, Yan-Heng Chen, Hsi-Chang Hsu, Chiang-Cheng Chang, Shih-Kuang Chiu
  • Publication number: 20140042638
    Abstract: A semiconductor package is provided, which includes: a soft layer having opposite first and second surfaces and first conductive through hole vias; a chip embedded in the soft layer and having an active surface exposed from the first surface of the soft layer; a support layer formed on the second surface of the soft layer and having second conductive through hole vias in electrical connection with the first conductive through hole vias; a first RDL structure formed on the first surface of the soft layer and electrically connected to the active surface of the chip; and a second RDL structure formed on the support layer and electrically connected to the first RDL structure through the first and second conductive through hole vias. The invention prevents package warpage by providing the support layer, and allows disposing of other packages or electronic elements by electrically connecting the RDL structures through the conductive through hole vias.
    Type: Application
    Filed: October 30, 2012
    Publication date: February 13, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hung-Wen Liu, Hsi-Chang Hsu, Hsin-Hung Chou, Hsin-Yi Liao, Chiang-Cheng Chang
  • Publication number: 20140035156
    Abstract: A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.
    Type: Application
    Filed: October 25, 2012
    Publication date: February 6, 2014
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Hsi-Chang Hsu, Hsin-Hung Chou, Hung-Wen Liu, Hsin-Yi Liao, Chiang-Cheng Chang