Abstract: A solar cell includes a semiconductor substrate, an emitter layer, at least one emitter contact region and at least one first electrode. The emitter layer is formed on at least one surface of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The emitter contact region is formed on portions of the emitter layer and has the same type of dopant as the emitter layer. The emitter contact region has a higher dopant concentration than the emitter layer. The first electrode is coupled with the emitter contact region.

Abstract: A photovoltaic power device is provided. The photovoltaic power device includes a donor substrate, a first emitting substrate; a second emitting substrate, a first anti-reflection layer, a first metal electrode, a second metal electrode and a second anti-reflection layer. In the photovoltaic power device, the first and the second emitting substrate are disposed in the opposite sides of the donor substrate to generate two electronic flows, and the first metal electrode is insulated from the second metal electrode by the second anti-reflection layer.

Abstract: A semiconductor device having a transistor and a storage capacitor. The transistor includes source and drain regions formed on a substrate. The storage capacitor is coupled to the transistor. The storage capacitor is formed from a bottle-shaped trench and having an Epi-Si layer grown inside the trench to form at least part of one of the source and drain regions. The Epi-Si layer can be selectively grown inside the trench from portions of the substrate such that the Epi-Si layer is used to define a bottle-shape for the trench.

Abstract: A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved ALCVD). Then, a high dielectric constant (high k) dielectric layer is formed overlying the collar dielectric and the bottom portion of the deep trench using atomic layer chemical vapor deposition (ALCVD). Thereafter, a conductive layer is filled into the deep trench and recessed to a predetermined depth. A portion of the dielectric layer and the high dielectric constant (high k) layer at the top of the deep trench are removed to complete the fabrication of the deep trench capacitor.

Abstract: A method for manufacturing a trench capacitor that comprises defining a semiconductor substrate, forming a trench with a lower region and an upper region in the semiconductor substrate, forming a buried conductive region around the lower region, forming a first insulating layer along sidewalls of the trench up to a level between the lower region and the upper region, forming a second insulating layer along the sidewalls of the trench at the upper region, the second insulating layer being separated from the first insulating layer by an intermediate region, and forming an oxide on the sidewalls of the trench at the intermediate region.

Abstract: A method for manufacturing a trench capacitor that comprises defining a semiconductor substrate, forming a trench with a lower region and an upper region in the semiconductor substrate, forming a buried conductive region around the lower region, forming a first insulating layer along sidewalls of the trench up to a level between the lower region and the upper region, forming a second insulating layer along the sidewalls of the trench at the upper region, the second insulating layer being separated from the first insulating layer by an intermediate region, and forming an oxide on the sidewalls of the trench at the intermediate region.

Abstract: A method of forming a trench capacitor is disclosed. After completion of the bottom electrode of the capacitor, a collar dielectric layer is directly formed on the sidewall of the deep trench using self-starved atomic layer chemical vapor deposition (self-starved ALCVD). Then, a high dielectric constant (high k) dielectric layer is formed overlying the collar dielectric and the bottom portion of the deep trench using atomic layer chemical vapor deposition (ALCVD). Thereafter, a conductive layer is filled into the deep trench and recessed to a predetermined depth. A portion of the dielectric layer and the high dielectric constant (high k) layer at the top of the deep trench are removed to complete the fabrication of the deep trench capacitor.

Abstract: A method of fabricating a shallow trench isolation is disclosed. First, a pad oxide layer and a polysilicon layer are formed on a silicon substrate. The pad oxide layer and the polysilicon layer are etched to expose parts of the substrate. Then the exposed parts of the substrate are oxidized to form an oxide layer. Next, the oxide layer is etched back to form an oxide spacer on the side wall of the polysilicon. Then, a shallow trench is formed by etching the partly exposed substrate. Next, a dielectric layer is formed to fill the shallow trench and then etched back by CMP to stop on the polysilicon layer. Finally, the pad oxide layer and the polysilicon layer are removed. As a result, oxide spacers on the side wall of the shallow trench are formed to eliminate the kink-effect.

Abstract: The present invention proposes a method for forming shallow trench isolation. Isolation trenches are firstly formed on a silicon substrate. High-density plasma oxide layer is used to fill the trenches. A layer of poly-silicon and a thin oxide layer are then deposited on the high-density plasma oxide layer. Selective poly-silicon chemical mechanical polishing is then used to form a self-align reverse poly mask on the surface of the shallow trenches filled with the high-density plasma oxide layer. The high-density plasma oxide layer is locally etched. Chemical mechanical polishing is then used to perform a planarization process on the surface. In the present invention, photolithography is not necessary in the planarization process of high-density plasma oxide layer. Manufacture cost is thus lower.

Abstract: A method of fabricating kink-effect-free shallow trench isolations is presented in this invention. First, a layer of silicon oxide and a layer of polysilican are sequentially deposited on a substrate, and then shallow trenches are formed, next thermal oxidation is performed to grow a passivation oxide layer on the exposed silicon, and then, a dielectric layer is formed to fill into the shallow trench. Finally, the dielectric layer on the active area is removed by using chemical mechanical polishing and the polysilicon layer provides for the etching end point. The level of shallow trench is higher than the level of active area as soon as stop polishing, because the polysilicon layer is polished faster than dielectric layer. It provides the passivation oxide on the sidewall of shallow trench to form spacers of the active area after removing the polysilicon of active area. It can provide a perfect shallow trench after an oxidation and etching process to avoid the kink effect.

Abstract: A method for forming a tungsten plug is disclosed herein. A TiSi.sub.2 layer is selectively formed in a contact hole by using chemical vapor deposition. Then, a TiN layer is formed on the surface of the contact hole and on the TiSi.sub.2 layer. Next, a tungsten layer is formed on the TiN layer and in the contact hole. A CMP is used to remove a portion of the tungsten layer and TiN layer for planarization.

Abstract: A method for forming a metal plug is provided. The method includes: a) forming a metal contact window in a substrate having an oxide layer; b) forming a barrier layer over a top surface of the oxide layer and a wall defining the metal contact window; c) forming a metal layer covering the barrier layer and filling up the metal contact window; d) removing a portion of the metal layer located above the barrier layer covering the top surface of the oxide layer by a chemical mechanical polishing method; and e) removing the barrier layer covering the top surface of the oxide layer by an etching method.

Abstract: An improved and new process for chemical/mechanical planarization (CMP) of a substrate surface, wherein the endpoint for the planarization process is detected by monitoring the temperature of the polishing pad with an infrared temperature measuring device, has been developed. The method allows endpoint to be detected in-situ at the polishing apparatus, without necessity to unload the substrate for visual inspection or performance of specialized, time-consuming, and costly thickness and/or surface topography measurements.