Abstract: A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away except for a portion surrounding the sidewall of the gate electrode to form a spacer. The tip of the spacer is at the same height as the upper surface of the liner layer and is lower than the upper surface of the gate electrode, therefore, resulting in an increase of the exposed area of the gate electrode surface.

Abstract: A method of fabricating a MOS transistor. A substrate has a gate formed thereon and a LDD is formed in the substrate beside the gate. A spacer is formed on the sidewall of the gate. A sacrificial layer is formed over the substrate to cover the gate and the spacer. A portion of the sacrificial layer is removed to expose a portion of the spacer. The exposed spacer is removed, such that a portion of the gate sidewall is exposed. The sacrificial layer is removed. A source/drain region is then formed in the substrate beside the spacer.

Abstract: A fabrication process for a polysilicon gate is described in which a silicon dioxide layer of various thicknesses is formed on the substrate and on the polysilicon gate with an overlying anti-reflection layer. The silicon dioxide layer is removed with enough silicon dioxide layer remaining to cover the sidewalls of the polysilicon gate and the silicon substrate before the removal of the anti-reflection layer. The sidewalls of the polysilicon gate and the silicon substrate are thus simultaneously protected during the removal of the anti-reflection layer.

Abstract: A fabrication method for a gate spacer. The method comprises provision of a substrate with a gate formed thereon, after which a SiNx spacer is formed on the gate sidewall. The substrate is then covered with a SiOx layer. A part of the SiOx layer is removed until the surface of the SiOx layer is lower than the top surface of the gate. A portion of the SiNx layer is removed to expose the top edge of the gate spacer and to increase the exposed area of the gate. The SiOx layer is consequently removed.