Abstract: A PV module includes a transparent substrate, a first solar cell unit, a crystalline silicon solar cell, and a spacer. The first solar cell unit is between the transparent substrate and the crystalline silicon solar cell, and the first solar cell unit includes a first electrode, a second electrode, and a I-III-VI semiconductor layer between the first electrode and the second electrode. The I-III-VI semiconductor layer includes at least gallium (Ga) and sulfur (S), and the energy gap thereof is more than that of crystalline silicon. Moreover, the crystalline silicon solar cell and the first solar cell unit are separated by the spacer.

Abstract: An open plant cultivation device has a container, a medium layer, a plant, and a separation layer. The container has an inner side surface, a sterile accommodation space, and an open growing space. The medium layer is disposed in the sterile accommodation space. The separation layer is disposed on the medium layer and adjacent to the inner side surface. The sterile accommodation space and the open growing space are isolated by the separation layer. A method for preparing an open plant cultivation device includes: putting a container in a sterile space; feeding a medium colloid into the container and immersing a part of a plant in the medium colloid; solidifying the medium into a medium layer; disposing a separation layer onto the medium layer to form the open plant cultivation device. The present invention has the open growing space and the effect of protecting the medium layer from contamination.

Abstract: A PV module includes a transparent substrate, a first solar cell unit, a crystalline silicon solar cell, and a spacer. The first solar cell unit is between the transparent substrate and the crystalline silicon solar cell, and the first solar cell unit includes a first electrode, a second electrode, and a I-III-VI semiconductor layer between the first electrode and the second electrode. The I-III-VI semiconductor layer includes at least gallium (Ga) and sulfur (S), and the energy gap thereof is more than that of crystalline silicon. Moreover, the crystalline silicon solar cell and the first solar cell unit are separated by the spacer.

Abstract: A real-time insulation detector for feeding a high-frequency low-voltage signal is electrically connected with a power system, and the power system includes a power circuit comprised of a main power circuit and plural branch circuits, a plurality of power transformers are arranged in the main power circuit and the plural branch circuits, and each current power transformer has a positive electrode point and a negative electrode point arranged on a low-voltage side thereof, the real-time insulation detector contains a central controller, a signal generator, a circuit selector, a plurality of detection circuits, plural first safety circuits, and plural second safety circuits. Thereby, the real-time insulation detector automatically feeds a high-frequency low-voltage detection signal, and when the power system runs in an uninterruptible power network, the central controller judges aging insulation comes from which one cable or component of the power system.

Abstract: Compositions and methods are provided for enhanced production of ethanol from fermentation of tobacco biomass. Nicotine resistant microorganisms are provided, as well as methods for making these nicotine resistant microorganisms. A biologically pure culture is provided of a nicotine resistant Saccharomyces cerevisiae strain or a mutant thereof having all the identifying characteristics thereof. Methods are provided for producing ethanol from fermentation of tobacco biomass in which the nicotine resistant microorganisms are used in the fermentation of the tobacco biomass, wherein a higher amount of ethanol can be produced from the fermentation. The nicotine resistant yeast strains of the present disclosure can improve ethanol production in tobacco biomass extract fermentations and shorten the fermentation time.

Abstract: A real-time insulation detector for feeding a high-frequency low-voltage signal is electrically connected with a power system, and the power system includes a power circuit comprised of a main power circuit and plural branch circuits, a plurality of power transformers are arranged in the main power circuit and the plural branch circuits, and each current power transformer has a positive electrode point and a negative electrode point arranged on a low-voltage side thereof, the real-time insulation detector contains a central controller, a signal generator, a circuit selector, a plurality of detection circuits, plural first safety circuits, and plural second safety circuits. Thereby, the real-time insulation detector automatically feeds a high-frequency low-voltage detection signal, and when the power system runs in an uninterruptible power network, the central controller judges aging insulation comes from which one cable or component of the power system.

Abstract: Compositions and methods are provided for enhanced production of ethanol from fermentation of tobacco biomass. Nicotine resistant microorganisms are provided, as well as methods for making these nicotine resistant microorganisms. A biologically pure culture is provided of a nicotine resistant Saccharomyces cerevisiae strain or a mutant thereof having all the identifying characteristics thereof. Methods are provided for producing ethanol from fermentation of tobacco biomass in which the nicotine resistant microorganisms are used in the fermentation of the tobacco biomass, wherein a higher amount of ethanol can be produced from the fermentation. The nicotine resistant yeast strains of the present disclosure can improve ethanol production in tobacco biomass extract fermentations and shorten the fermentation time.

Abstract: A method of repairing defect in a superconducting film, a method of coating a superconducting film, and a superconducting film formed by the method are prepared. The method of repairing defect includes detecting the superconducting film during a manufacturing process thereof. When a defect therein is detected, a repairing structure with superconductivity is formed on a position of the defect.

Abstract: A merchandise recommendation method for multiple users used in a merchandise recommendation system including a user database, a merchandise database, a data transmission module, a processing module and a memory is provided. The merchandise recommendation method includes the steps outlined below. The processing module receives participant information and target merchandise information from a remote originator host. The processing module retrieves corresponding user information from the user database according to the participant information. The processing module retrieves corresponding merchandise information from the merchandise database according to the target merchandise information. The processing module analyzes social influence information and preference information included in the user information and analyzes the merchandise information to generate an analysis result. The processing module generates composite merchandise recommendation information according to the analysis result.

Abstract: A portable electronic device switches between antennas in order to decrease specific absorption rate (SAR). When the portable electronic device performs wireless communication, a sensor detects a distance between an object under test and the portable electronic device. The sensor sends a message to a control circuit, and the control circuit switches to a different antenna to decrease SAR.

Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

Abstract: Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

Abstract: In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.

Abstract: In accordance with a method for generating a trial placement plan for an IC having two or more identical modules, a floor plan reserves a separate area of identical size and shape for each of the identical modules, one of which is designated a “master module” and the others designated “clone modules”. A placement and routing (P&R) tool initially places all of the cell instances of the clone modules at the center of their reserved areas. The P&R tool then employs a conventional placement algorithm to iteratively adjust positions of cell instances of all other modules, including the master module within their reserved areas in a manner that tries to minimize net lengths. The P&R tool copies the placement within the master module area into the clone module areas either after every N>0 iterations of the placement algorithm and/or after the placement algorithm has completed placement for the master module area.

Abstract: Low leakage and low resistance plugs for a memory device and the manufacturing method for the plugs includes a doped polysilicon layer first deposited at contact nodes and bit-line contacts inside the memory to form a low leakage interface. A low contact resistance imbedded tungsten plug is subsequently deposited on the polysilicon layer to form a low contact resistance imbedded tungsten plug in concavities at the contact nodes and bit-line contacts. Excess material is etched to leave double layer plugs at the contact nodes and bit-line contacts that constitute low leakage and low contact resistance memory plugs.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: When generating a layout for an integrated; circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.

Abstract: An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition.

Abstract: Low leakage and low resistance plugs for a memory device and the manufacturing method for the plugs includes a doped polysilicon layer first deposited at contact nodes and bit-line contacts inside the memory to form a low leakage interface. A low contact resistance imbedded tungsten plug is subsequently deposited on the polysilicon layer to form a low contact resistance imbedded tungsten plug in concavities at the contact nodes and bit-line contacts. Excess material is etched to leave double layer plugs at the contact nodes and bit-line contacts that constitute low leakage and low contact resistance memory plugs.

Abstract: When generating a layout for an integrated circuit (IC) based on a netlist design, a trial layout which need only satisfy the various spatial, power and other constraints, but need not satisfy the layout's timing constraints, is quickly produced. The trial layout acts as a basis for estimating sizes and positions of substrate areas needed to accommodate various modules of the IC and for estimating delays through various signal paths having timing constraints. After producing the trial layout, the IC design is divided into several partitions with modules being grouped into partitions in accordance with their proximity to one another in the trial layout. A floor plan is created which imposes spatial constraints on each partition based on the estimated size and position within the trial layout of the modules forming the partition. A timing budget is also created which allocates portions of each timing constraint to the partitions based on the time delay estimates derived from the trial layout.