Abstract: A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool.

Abstract: A method for optimizing an inspection recipe of a defect inspection tool is described. A substrate having thereon intentional defects and locating patterns beside the intentional defects is provided. The defect inspection tool is used to detect the intentional defects with an inspection recipe and obtain the distribution of undetected or partially detected intentional defects. The locating patterns are utilized to locate the undetected or partially detected intentional defects and thereby determine the type(s) of the undetected or partially detected intentional defects. The inspection recipe is modified according to the type(s) of the undetected or partially detected intentional defects in a manner such that there is a minimal number of undetected or partially detected intentional defects under the inspection of the defect inspection tool.

Abstract: An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region.

Abstract: The method for in-line monitoring a wafer is described as follows. A wafer is provided, and at least one inspection structure is then formed on the wafer in the following steps. An N-well region and a P-well region are formed in the wafer, wherein the N-well region and the P-well region are separated from each other. A gate on each of the N-well region and the P-well region is formed. A P-type doped region is respectively formed in the N-well region and in the P-well region at both sides of the gates. A first contact plug is formed on each P-type doped region, and second contact plug is formed on each gate. Afterwards, a defect inspection is conducted utilizing an electron beam inspection (EBI) system, such that a short between each first contact plug and each gate is determined.

Abstract: A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection.

Abstract: A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection.