Abstract: Disclosed in the present invention is an optimized cell transplant. The optimized cell transplant is formed by performing gene induction and modification on a mesenchymal stem cell in the form of a small molecule and protein composition. The expression levels of CD200 gene, Galectin-9 gene and VISTA gene can be increased synchronously after cell culture. Vector virus infection and plasmid transfection are not required in the cell preparation process, so that high biological safety and great clinical application value of cells are achieved.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: Information handling system thermal management of processing components, such as CPU, GPU and/or memory, by a liquid cooling system is protected by a leak detection enclosure having a leak detection sensor disposed in an interior. The leak detection enclosure has a frame coupled to a cold plate that encloses the leak detection sensor and cooling fluid hose fittings so that leaked fluid is trapped within the enclosure for detection by the leak detection sensor. A planar cover couples to the frame upper side over the leak detection circuit and the cooling fluid hose fittings to provide ready assembly and an inexpensive adaptable form factor.

Abstract: An optical switch structure includes at least one optical input port and at least one optical output port. The optical switch structure also includes an optical waveguide structure including a waveguide core and a waveguide cladding The optical waveguide structure is optically coupled to the at least one optical input port and the at least one optical output port. The waveguide core includes a first material characterized by a first index of refraction and a first electro-optic coefficient and the waveguide cladding includes a second material characterized by a second index of refraction less than the first index of refraction and a second electro-optic coefficient greater than the first electro-optic coefficient.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: Provided herein are antigenic molecules that can be used to generate antibodies capable of binding to a vitamin D derivative, such as 25-hydroxyvitamin D2 and/or 25-hydroxyvitamin D3, or a 25-hydroxyvitamin D analog, such as a vitamin D-C22 immunogenic molecule or compound. Antibodies produced using these antigenic molecules, and related antigenic compounds, are also described. In addition, disclosed herein are methods for detecting vitamin D deficiency in a subject, methods for treating a subject suspected of having a vitamin D deficiency, methods for monitoring progression of vitamin D deficiency in a subject, and methods for monitoring treatment of vitamin D deficiency in a subject in need thereof. The methods involve the detection or quantification of 25-hydroxyvitamin D2 and D3.

Abstract: The present invention provides a display method and structure of an intelligent memory, which is a temperature detection method and structure, which is used in a memory device, of which the memory device includes a substrate, a thermal sensor, a plurality of memory chips, a micro-control unit, and a notification module. The steps include generating at least one temperature data according to the temperature of the plurality of memory chips sensed by the thermal sensor, transmitting the at least one temperature data to the micro-control unit, and the micro-control unit determining whether the at least one temperature data exceeds a first threshold, When at least one temperature data exceeds the first threshold, the micro-control unit transmits a first control signal to a notification module, which can further be used for the method and structure for displaying real-time information.

Abstract: An optical switch structure includes a substrate, a first electrical contact, a first material having a first conductivity type electrically connected to the first electrical contact, a second material having a second conductivity type coupled to the first material, and a second electrical contact electrically connected to the second material. The optical switch structure also includes a waveguide structure disposed between the first electrical contact and the second electrical contact and comprising a waveguide core coupled to the substrate and including a first material characterized by a first index of refraction and a first electro-optic coefficient and a waveguide cladding at least partially surrounding the waveguide core and including a second material characterized by a second index of refraction and a second electro-optic.

Abstract: Securing a riser cage and/or electronic components coupled thereto within an information handling system can be accomplished using a riser cage apparatus. The riser cage may be configured to removably secure the electronic components to a surface of the information handling system using one or more fasteners configured to couple the riser cage to a surface of a chassis. The one or more fasteners may comprise a protrusion configured to engage a pin coupled to the surface. The protrusion of the one or more fasteners may be movable relative to the riser cage between a first locked position in which the pin coupled to the surface is engaged by the protrusion and a second unlocked position in which the pin coupled to the surface is not engaged by the protrusion.

Abstract: The invention discloses a vessel automatic berthing wireless charging integrated system and operating method thereof. The invention comprises a charging barge and at least one vessel. The charging barge comprises a power, a distribution board and a locking module control system, and every vessel comprises an automatic pilot system, a vessel controlling system and a wireless power receiving module. A bow berthing module of the present invention moors the vessel. After a guiding structure of the bow berthing module straightly aligns bow direction of the vessel, a wireless power supplying module of a side berthing module matches with the wireless power receiving module then charges the vessel.

Abstract: An optical switch structure includes a substrate, a first electrical contact, a first material having a first conductivity type electrically connected to the first electrical contact, a second material having a second conductivity type coupled to the first material, and a second electrical contact electrically connected to the second material. The optical switch structure also includes a waveguide structure disposed between the first electrical contact and the second electrical contact and comprising a waveguide core coupled to the substrate and including a first material characterized by a first index of refraction and a first electro-optic coefficient and a waveguide cladding at least partially surrounding the waveguide core and including a second material characterized by a second index of refraction and a second electro-optic.

Abstract: Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.

Abstract: A 3D display system and a 3D display method are provided. The 3D display system includes a 3D display, a memory, and a processor. The processor is coupled to the 3D display and the memory and is configured to execute the following steps. As a first type application program is executed, an image content of the first type application program is captured, and a stereo format image is generated according to the image content of the first type application program. The stereo format image is delivered to a runtime complying with a specific development standard through an application program interface complying with the specific development standard. A display frame processing associated with the 3D display is performed on the stereo format image through the runtime, and a 3D display image content generated by the display frame processing is provided to the 3D display for displaying.

Abstract: A temperature regulating nylon fiber includes a fiber body and a phase change composition. The phase change composition is doped in the fiber body and includes 450 parts by weight to 550 parts by weight of a polytetrahydrofuran derivative and 5 parts by weight to 20 parts by weight of a succinic anhydride derivative. Based on 100 parts by weight of the temperature regulating nylon fiber, a content of the phase change composition is between 6 parts by weight and 12 parts by weight.

Abstract: A repair method of a memory includes dividing a plurality of general bits into a plurality of first groups and dividing a plurality of redundancy bits into a plurality of second groups. When one of the plurality of first groups has a defective bit, one of the plurality of second groups is selected to replace the first group which has the defective bit. Because the repair method uses a group as a repair unit, a repair circuit is simpler and smaller and a processing speed of the repair circuit is faster.

Abstract: A full load test system of an electrical power converter and the test method thereof is disclosed. The full load test method of the electrical power converter comprises the following steps: (a) providing a power converter under test (PCUT); (b) configuring the PCUT in/on a test circuit; (c) serially connecting the PCUT with at least one bidirectional power converter in the test circuit; (d) connecting the test circuit to an alternating current low voltage three-phase power source; and (e) performing a test of the PCUT under full-load condition.

Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.