Abstract: In one embodiment, a method includes connecting, via a first interface of a controller card, a multiplexer of the controller card to a central processing unit (CPU) of the controller card. The method also includes connecting, via an interface of a first remote card, the multiplexer of the controller card to the first remote card. The method further includes interconnecting, by the multiplexer, the first interface of the controller card to the interface of the first remote card.

Abstract: In one embodiment, a method includes establishing a connection between a hardware switch and a console port, connecting the console port to a first central processing unit (CPU) using the hardware switch, and receiving, from the console port, a first character stream. The method also includes detecting, by the hardware switch, a first special character within the first character stream. The method further includes connecting, by the hardware switch, the console port to a second CPU in response to detecting the first special character within the first character stream.

Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.

Abstract: A bit line power implementing circuit is provided, the bit line power implementing circuit has a bit line discharge oscillator to convert the supply voltage to a pulse; a decoder coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency; a first and a second counters, coupled to the decoder, and receiving the first and the second pulses respectively, and outputting a signal proportional to an average and a minimum read currents respectively; a divider outputting a read current ratio of the average read current to the minimum read current; and a multiplier for multiplying the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.

Abstract: A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to an inverting state in response to a potential of the one or more input signals. Each transistor in the sensing circuit may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation.

Abstract: A process monitoring circuit may be used to determine appropriate voltage for integrated circuits including a non-volatile memory. The process monitoring circuit includes a bandgap reference, a clock generator, a negative bias circuit, a temperature insensitive oscillator, a low dropout voltage regulator, a counter, a comparison circuit, and a charge. The process monitoring circuit may also include a pulse width generator. The process monitoring circuit is able to determine the process corner of which a monitored circuit belongs to and generate an output voltage according to the process corner of the monitored circuit.