Patents by Inventor Hsi-Yuan Hsu

Hsi-Yuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050041564
    Abstract: A recording apparatus includes a microphone for receiving sound waves and generating a corresponding audio signal, a signal module for providing corresponding sound data according to the audio signal, and an optical recording module for writing the data optically onto optical storage media. The optical recording module is only for writing the data optically into the optical storage media.
    Type: Application
    Filed: September 18, 2003
    Publication date: February 24, 2005
    Inventors: Hsi-Yuan Hsu, Chun-Hsien Lee
  • Patent number: 6502159
    Abstract: Techniques for improving overall data throughput in a computer system, especially during the playing of movies from CD-ROMs provides for a direct flow of data between the CD-ROM and the MPEG card, greatly reducing system memory usage and bus utilization. Control circuitry is responsive to signals from the CPU, which signals specify whether data from the CD-ROM can be sent directly to the MPEG decoder circuit or needs to be sent over the buses to the system memory. Accordingly, different transmission paths are used, depending on the attribute and destination of the data in order to reduce unnecessary data flow in the system and unnecessary consumption of system resources.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: December 31, 2002
    Assignees: Acer Incorporated, Acer Laboratories Inc.
    Inventors: Te-Chih Chuang, Hsueh-Wei Huang, Hsi-Yuan Hsu
  • Patent number: 5229758
    Abstract: A display device controller with improved read performance comprises video memory, a video display control unit, video processing logic, a write buffer and a read buffer. The write buffer and read buffer are coupled between a CPU and the video memory for transferring information between the CPU and video memory. In the preferred embodiment, the read buffer further comprises an address latch, a control circuit, a first buffer, a second buffer, a multiplexer and a counter. The control circuit stores addresses in the address latch, reads video memory, and stores the data in the first and second buffers. The control circuit determines the output to the CPU by controlling the multiplexer. The control circuit is also responsive to the counter and the read buffer is partially disabled if the miss rate is a high to reduce the negative consequences of the additional information read by the control circuit.
    Type: Grant
    Filed: September 5, 1991
    Date of Patent: July 20, 1993
    Assignee: ACER Incorporated
    Inventor: Hsi-Yuan Hsu