Patents by Inventor Hsiang Chang
Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220102582Abstract: A semiconductor structure includes a carrier, a bonding structure, a semiconductor stack, a supporting element and a bridge layer. The bonding structure is on the carrier and has an upper surface. The semiconductor stack is on the bonding structure. The supporting element is on the bonding structure and has a side wall. The bridge layer has a first portion directly connected to the supporting element, a second portion connected to the first portion and a third portion connected to the second portion. The second portion and the third portion of the bridge layer are suspended above the upper surface of the bonding structure. The first portion of the bridge layer directly contacts the side wall of the supporting element.Type: ApplicationFiled: December 14, 2021Publication date: March 31, 2022Inventors: Yung-Fu CHANG, Fan-Lei WU, Shih-Chang LEE, Wen-Luh LIAO, Hung-Ta CHENG, Chih-Chaing YANG, Yao-Ru CHANG, Yi HSIAO, Hsiang CHANG
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Patent number: 11263192Abstract: Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises generating a context data tree for each variable in a plurality of variables based on a received input; determining data folding points for each generated context data tree; conducting a hyper-folding process on the determined data folding points in each context data tree, wherein the hyper-folding process converts each generated context data tree into a single data tree; and automatically loading the single data tree into an application.Type: GrantFiled: November 18, 2019Date of Patent: March 1, 2022Assignee: International Business Machines CorporationInventors: Chiwen Chang, Hsiang Chang, Ming Jyh Hsieh
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Patent number: 11227975Abstract: A semiconductor structure includes a carrier having a surface, a supporting element, a semiconductor stack and a bridge layer. The supporting element is on the surface. The semiconductor stack is on the surface and has a side surface. The bridge layer includes a first portion connecting to the supporting element, a second portion, and a third portion connecting to the semiconductor stack. The second portion is extended from the third portion toward the first portion and is protruded from the side surface.Type: GrantFiled: August 23, 2019Date of Patent: January 18, 2022Assignee: Epistar CorporationInventors: Yung-Fu Chang, Fan-Lei Wu, Shih-Chang Lee, Wen-Luh Liao, Hung-Ta Cheng, Chih-Chaing Yang, Yao-Ru Chang, Yi Hsiao, Hsiang Chang
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Publication number: 20210149864Abstract: Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises generating a context data tree for each variable in a plurality of variables based on a received input; determining data folding points for each generated context data tree; conducting a hyper-folding process on the determined data folding points in each context data tree, wherein the hyper-folding process converts each generated context data tree into a single data tree; and automatically loading the single data tree into an application.Type: ApplicationFiled: November 18, 2019Publication date: May 20, 2021Inventors: Chiwen Chang, Hsiang Chang, Ming Jyh Hsieh
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Publication number: 20200365769Abstract: A semiconductor device is provided, which includes a base, a semiconductor structure and a conductive reflective structure. The base has a first surface and a second surface opposite to the first surface. The semiconductor structure is located on the first surface. The conductive reflective structure is located on the second surface and includes a metal oxide structure and a metal structure. The metal oxide structure is located between the metal structure and the base. The metal oxide structure physically contacts the second surface.Type: ApplicationFiled: May 15, 2020Publication date: November 19, 2020Inventors: Yao-Ru CHANG, Wen-Luh LIAO, Yung-Fu CHANG, Hsiang CHANG, Meng-Yang CHEN, Yun-Hsin PANG, Yi HSIAO
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Publication number: 20200075807Abstract: A semiconductor structure includes a carrier having a surface, a supporting element, a semiconductor stack and a bridge layer. The supporting element is on the surface. The semiconductor stack is on the surface and has a side surface. The bridge layer includes a first portion connecting to the supporting element, a second portion, and a third portion connecting to the semiconductor stack. The second portion is extended from the third portion toward the first portion and is protruded from the side surface.Type: ApplicationFiled: August 23, 2019Publication date: March 5, 2020Inventors: Yung-Fu CHANG, Fan-Lei WU, Shih-Chang LEE, Wen-Luh LIAO, Hung-Ta CHENG, Chih-Chaing YANG, Yao-Ru CHANG, Yi HSIAO, Hsiang CHANG
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Patent number: 8179138Abstract: A cathode ray tube (CRT) test system for testing a CRT device is disclosed. The CRT test system comprises a connecting device, a power module, a control module, a first test module, and an illumination module. The connecting device detachably and electrically connects with the CRT device; the power module electrically connects with the connecting device; the control module electrically connects with the connecting device; and the control module comprises test program. After the CRT device receives a control signal transmitted from the test program, the CRT device generates a response signal and transmits the response signal to the first test module. When the first test module detects that the control signal and the response signal fit in with a first test signal status, the illumination module displays a first light sign; when the control signal and the response signal do not fit in with the first test signal status, the illumination module displays a second light sign.Type: GrantFiled: November 20, 2009Date of Patent: May 15, 2012Assignee: Wistron CorporationInventors: Hsiang Chang, Cheng-Hsuan Tsai, Ming-Chang Liu
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Publication number: 20100295949Abstract: A cathode ray tube (CRT) test system for testing a CRT device is disclosed. The CRT test system comprises a connecting device, a power module, a control module, a first test module, and an illumination module. The connecting device detachably and electrically connects with the CRT device; the power module electrically connects with the connecting device; the control module electrically connects with the connecting device; and the control module comprises test program. After the CRT device receives a control signal transmitted from the test program, the CRT device generates a response signal and transmits the response signal to the first test module. When the first test module detects that the control signal and the response signal fit in with a first test signal status, the illumination module displays a first light sign; when the control signal and the response signal do not fit in with the first test signal status, the illumination module displays a second light sign.Type: ApplicationFiled: November 20, 2009Publication date: November 25, 2010Applicant: Wistron CorporationInventors: Hsiang Chang, Cheng-Hsuan Tsai, Ming-Chang Liu
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Publication number: 20070117407Abstract: The present invention provides a method for forming substrates for MOS (metal oxide semiconductor) transistor, comprising the following steps: (A) In a reduced-pressure environment having a pressure lower than 1×10?6 Torr, a base for accomplishing the surface reconstruction and a solid-state metal oxide source is provided, wherein the solid-state metal oxide source is chosen from the group consisting of the following: hafnium oxide, aluminum oxide, scandium oxide, yttrium oxide, titanium oxide, gallium gadolinium oxide and metal oxides of rare earth elements; and (B) vaporize the solid-state metal oxide source in order to make the solid-state metal oxide source become a metal oxide molecular beam and, in a working substrate temperature that is required to achieve an amorphous state of a first metal oxide film, deposit on the base having an amorphous state so as to further fabricate a substrate for MOS transistors.Type: ApplicationFiled: November 22, 2006Publication date: May 24, 2007Applicant: National Tsing Hua UniversityInventors: Juei-Nai Kwo, Ming-Hwei Hong, Wei Lee, Hsiang Chang, Yan Wu, Kun Lee, Yi Lee
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Patent number: 6175496Abstract: A heat-dissipating device is adapted for dissipating heat inside an equipment housing which includes a housing part having upright first and second side walls and a bottom wall. The first and second side walls extend transverse to each other such that the first and second side walls and the bottom wall cooperate to form a corner portion of the housing part. The heat-dissipating device includes a remote heat-dissipating unit adapted to be disposed in the equipment housing and having a heat transfer plate, a heat exchanger pipe connected to the heat transfer plate, and a heat sink coupled to the heat exchanger pipe, and a fan unit adapted to be disposed in the corner portion.Type: GrantFiled: December 6, 1999Date of Patent: January 16, 2001Assignee: Compal Electronics, Inc.Inventors: Jen-Hao Liu, Hsiang Chang, Hsiang-Wei Chen, Shih-Wei Lin