Patents by Inventor Hsiang-Che Hsu

Hsiang-Che Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for testing chips
    Patent number: 8694839
    Abstract: A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: April 8, 2014
    Assignee: VIA Technologies Inc.
    Inventors: Hsiang-Che Hsu, Bowei Hsieh
  • METHOD AND SYSTEM FOR TESTING CHIPS
    Publication number: 20110047420
    Abstract: A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip.
    Type: Application
    Filed: November 3, 2010
    Publication date: February 24, 2011
    Inventors: Hsiang-Che Hsu, Bowei Hsieh
  • Method and system for testing chips
    Patent number: 7853843
    Abstract: Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: December 14, 2010
    Assignee: VIA Technologies Inc.
    Inventors: Hsiang-Che Hsu, Bowei Hsieh
  • METHOD AND SYSTEM FOR TESTING CHIPS
    Publication number: 20080104463
    Abstract: Method and related system for testing a chip with high speed I/O functions are provided. The testing method of a chip includes the steps of: receiving a testing signal from a low speed bus; then transmitting the testing signal according to a transmission control signal; then receiving the testing signal according to a receiving control signal; and comparing the transmitted testing signal and the received testing signal to identify the I/O functions of the chip.
    Type: Application
    Filed: January 29, 2007
    Publication date: May 1, 2008
    Inventors: Hsiang-Che Hsu, Bowei Hsieh