Patents by Inventor Hsiang-Chen Lee
Hsiang-Chen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
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Patent number: 10720440Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.Type: GrantFiled: March 21, 2018Date of Patent: July 21, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
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Publication number: 20180211966Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.Type: ApplicationFiled: March 21, 2018Publication date: July 26, 2018Applicant: United Microelectronics Corp.Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
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Patent number: 9966382Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.Type: GrantFiled: August 16, 2016Date of Patent: May 8, 2018Assignee: United Microelectronics Corp.Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
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Publication number: 20180053771Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.Type: ApplicationFiled: August 16, 2016Publication date: February 22, 2018Applicant: United Microelectronics Corp.Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
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Patent number: 9466497Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.Type: GrantFiled: January 12, 2016Date of Patent: October 11, 2016Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kuo-Lung Li, Ping-Chia Shih, Hsiang-Chen Lee, Yu-Chun Chang, Chia-Wen Wang, Meng-Chun Chen, Chih-Yang Hsu
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Patent number: 9397202Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.Type: GrantFiled: March 23, 2016Date of Patent: July 19, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
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Publication number: 20160204230Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.Type: ApplicationFiled: March 23, 2016Publication date: July 14, 2016Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
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Patent number: 9331183Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.Type: GrantFiled: June 3, 2013Date of Patent: May 3, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
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Patent number: 9129852Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.Type: GrantFiled: August 11, 2014Date of Patent: September 8, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsiang-Chen Lee, Shao-Nung Huang, Wei-Pin Huang, Kuo-Lung Li, Ling-Hsiu Chou, Ping-Chia Shih
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Patent number: 9040423Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.Type: GrantFiled: July 17, 2013Date of Patent: May 26, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
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Publication number: 20150024598Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first area with a first poly layer and a second area with a second poly layer is provided. A nitride HM film is then deposited above the first poly layer of a first device in the first area and above the second poly layer in the second area. Afterwards, a first patterned passivation is formed on the nitride HM film in the first area to cover the nitride HM film and the first device, and a second patterned passivation is formed above the second poly layer in the second area. The second poly layer in the second area is defined by the second patterned passivation.Type: ApplicationFiled: July 17, 2013Publication date: January 22, 2015Inventors: Wan-Fang Chung, Ping-Chia Shih, Hsiang-Chen Lee, Che-Hao Chang, Jhih-Long Lin, Wei-Pin Huang, Shao-Nung Huang, Yu-Cheng Wang, Jaw-Jiun Tu, Chung-Che Huang
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Patent number: 8921185Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.Type: GrantFiled: April 17, 2014Date of Patent: December 30, 2014Assignee: United Microelectronics CorporationInventors: Hsiang-Chen Lee, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
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Publication number: 20140353739Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.Type: ApplicationFiled: June 3, 2013Publication date: December 4, 2014Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
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Publication number: 20140227844Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.Type: ApplicationFiled: April 17, 2014Publication date: August 14, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Hsiang-Chen LEE, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang
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Publication number: 20140091383Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Applicant: United Microelectronics Corp.Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
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Patent number: 8629025Abstract: A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions.Type: GrantFiled: February 23, 2012Date of Patent: January 14, 2014Assignee: United Microelectronics Corp.Inventors: Ko-Chi Chen, Ping-Chia Shih, Chih-Ming Wang, Chi-Cheng Huang, Hsiang-Chen Lee
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Patent number: 8546871Abstract: A non-volatile memory cell includes a substrate, two charge trapping structures, a gate oxide layer, a gate and two doping regions. The charge trapping structures are disposed on the substrate separately. The gate oxide layer is disposed on the substrate between the two charge trapping structures. The gate is disposed on the gate oxide layer and the charge trapping structures, wherein the charge trapping structures protrude from two sides of the gate. The doping regions are disposed in the substrate at two sides of the gate.Type: GrantFiled: July 6, 2011Date of Patent: October 1, 2013Assignee: United Microelectronics Corp.Inventors: Chi-Cheng Huang, Ping-Chia Shih, Chih-Ming Wang, Chun-Sung Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
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Patent number: 8546226Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, wherein the method comprises steps as following: a pad oxide layer and a first hard mask layer are sequentially formed on a substrate. The pad oxide layer and the first hard mask layer are then etched through to form an opening exposing a portion of the substrate. Subsequently, an oxide-nitride-oxide (ONO) structure with a size substantially less than or equal to the opening is formed to coincide with the portion of the substrate exposed from the opening.Type: GrantFiled: July 25, 2011Date of Patent: October 1, 2013Assignee: United Microelectronics Corp.Inventors: Chih-Ming Wang, Ping-Chia Shih, Chun-Sung Huang, Chi-Cheng Huang, Hsiang-Chen Lee, Chih-Hung Lin, Yau-Kae Sheu
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Publication number: 20130234252Abstract: An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.Type: ApplicationFiled: March 6, 2012Publication date: September 12, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Hsiang-Chen LEE, Ping-Chia Shih, Ke-Chi Chen, Chih-Ming Wang, Chi-Cheng Huang