Patents by Inventor Hsiang-Chi Cheng

Hsiang-Chi Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240265956
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 8, 2024
    Inventors: Hsiang-Chi CHENG, Shyh-Bin KUO, Yi-Cheng LAl, Chung-Hung CHEN, Shih-Hsien YANG, Yu-Chih WANG, Kuo-Hsiang CHEN
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Patent number: 11687757
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: June 27, 2023
    Assignee: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Publication number: 20230154511
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Application
    Filed: May 17, 2022
    Publication date: May 18, 2023
    Inventors: Hsiang-Chi CHENG, Shyh-Bin KUO, Yi-Cheng LAI, Chung-Hung CHEN, Shih-Hsien YANG, Yu-Chih WANG, Kuo-Hsiang CHEN
  • Patent number: 11610921
    Abstract: A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: March 21, 2023
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Yi-Cheng Lai, Sin-Jie Wang, Shyh-Bin Kuo, Kuo-Hsiang Chen, Yu-Chih Wang, Chung-Hung Chen
  • Patent number: 11600912
    Abstract: An antenna device includes a substrate, a chip, and an antenna. The chip is disposed on the substrate, and the chip has at least two pads. The antenna is disposed on the substrate, and the chip is disposed between the substrate and the antenna. The antenna has a first bonding line segment and a second bonding line segment electrically connected to the at least two pads respectively. The first bonding line segment is located at an outermost coil of the antenna, and is disposed across a short side direction of the chip in a manner of completely covering one of the at least two pads. The second bonding line segment is located at an innermost coil of the antenna, and is disposed across the short side direction of the chip in a manner of completely covering another of the at least two pads.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: March 7, 2023
    Assignees: Au Optronics Corporation, SES RFID Solutions GmbH
    Inventors: Chung-Hung Chen, Yi-Cheng Lai, Hsiang-Chi Cheng, Shyh-Bin Kuo, Martin Jeffrey Scattergood
  • Publication number: 20220188589
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Applicant: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Patent number: 11342284
    Abstract: A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 24, 2022
    Assignee: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Chung-Hung Chen
  • Patent number: 11301740
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: April 12, 2022
    Assignee: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Publication number: 20210295787
    Abstract: The present disclosure relates to a display device including a backlight circuit, a processing circuit, and a clock generation circuit. The backlight circuit is configured to be driven in response to a control signal. The processing circuit is electrically connected to the backlight circuit and is configured to generate a voltage signal and the control signal. The clock generating circuit is electrically connected to the processing circuit to receive the voltage signal. The processing circuit is configured to adjust the control signal according to a clock frequency of the clock signal.
    Type: Application
    Filed: December 9, 2020
    Publication date: September 23, 2021
    Inventors: Sin-Jie WANG, Kuo-Hsiang CHEN, Hsiang-Chi CHENG, Ya-Ting LIN, Shyh-Bin KUO, Yi-Cheng LAI, Yu-Chih WANG, Chung-Hung CHEN
  • Publication number: 20210184342
    Abstract: An antenna device includes a substrate, a chip, and an antenna. The chip is disposed on the substrate, and the chip has at least two pads. The antenna is disposed on the substrate, and the chip is disposed between the substrate and the antenna. The antenna has a first bonding line segment and a second bonding line segment electrically connected to the at least two pads respectively. The first bonding line segment is located at an outermost coil of the antenna, and is disposed across a short side direction of the chip in a manner of completely covering one of the at least two pads. The second bonding line segment is located at an innermost coil of the antenna, and is disposed across the short side direction of the chip in a manner of completely covering another of the at least two pads.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 17, 2021
    Applicants: Au Optronics Corporation, SES RFID Solutions GmbH
    Inventors: Chung-Hung Chen, Yi-Cheng Lai, Hsiang-Chi Cheng, Shyh-Bin Kuo, Martin Jeffrey Scattergood
  • Publication number: 20210182643
    Abstract: An integrated circuit, a wireless communication card and a wiring structure of an identification mark are provided. The integrated circuit includes a power supply wiring, a ground wiring and at least one identification mark pattern. Each identification mark pattern has a first conductive wiring and a second conductive wiring that overlap each other, wherein the first conductive wiring is electrically connected to the power wiring, and the second conductive wiring is electrically connected to the ground wiring.
    Type: Application
    Filed: October 28, 2020
    Publication date: June 17, 2021
    Applicant: Au Optronics Corporation
    Inventors: Shyh-Bin Kuo, Hsiang-Chi Cheng, Sin-Jie Wang, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsing Hung
  • Publication number: 20210183908
    Abstract: A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.
    Type: Application
    Filed: September 26, 2020
    Publication date: June 17, 2021
    Applicant: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Yi-Cheng Lai, Sin-Jie Wang, Shyh-Bin Kuo, Kuo-Hsiang Chen, Yu-Chih Wang, Chung-Hung Chen
  • Publication number: 20210134738
    Abstract: A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines.
    Type: Application
    Filed: September 11, 2020
    Publication date: May 6, 2021
    Applicant: Au Optronics Corporation
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Chung-Hung Chen