Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.

Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.

Abstract: A level shifter for high-speed level shifting includes a first P-channel transistor, comprising a gate coupled to a drain, and a source coupled to a system voltage; a second P-channel transistor, comprising a gate coupled to the gate of the first P-channel transistor, and a source coupled to the system voltage; a first N-channel transistor, comprising a drain coupled to the drain of the first P-channel transistor, and a source coupled to a ground level; and a second N-channel transistor, comprising a drain coupled to a drain of the second P-channel transistor, and a source coupled to the ground level; wherein the first N-channel transistor and the second N-channel transistor are low-threshold-voltage transistors or native transistors.

Abstract: A level shifter for high-speed level shifting includes a first P-channel transistor, comprising a gate coupled to a drain, and a source coupled to a system voltage; a second P-channel transistor, comprising a gate coupled to the gate of the first P-channel transistor, and a source coupled to the system voltage; a first N-channel transistor, comprising a drain coupled to the drain of the first P-channel transistor, and a source coupled to a ground level; and a second N-channel transistor, comprising a drain coupled to a drain of the second P-channel transistor, and a source coupled to the ground level; wherein the first N-channel transistor and the second N-channel transistor are low-threshold-voltage transistors or native transistors.

Abstract: A phase-locked loop apparatus (PLL apparatus) and a tuning voltage providing circuit thereof are provided. The PLL apparatus is for receiving an input signal and producing an output signal according to the received input signal. The PLL apparatus includes a voltage-controlled oscillator (VCO), a loop filter and a tuning voltage providing circuit. The VCO receives a control voltage and produces the output signal according to the received control voltage. The loop filter has a resistor-capacitor network and the network receives the control voltage and is coupled to a reference voltage. The tuning voltage providing circuit receives the output signal and the input signal and provides a tuning voltage to the resistor-capacitor network according to the input signal and the output signal.

Abstract: A pre-driver and a differential signal transmitter using the same are provided. The pre-driver includes a latch circuit and a driver buffer. The latch circuit includes latch units, first inverters, and second inverters. The latch units are coupled in series between a pair of differential input terminals and a pair of differential latch terminals, receive a pair of differential input signals through the pair of differential input terminals, and latch the pair of differential input signals according to a clock signal to provide a pair of differential latch signals through the pair of differential latch terminals. The first and second inverters are respectively coupled in series between the pair of differential latch terminals and a pair of differential output terminals. The driver buffer is coupled to the pair of differential output terminals to receive a pair of differential output signals, and accordingly provides a pair of differential pre-driver output signals.

Abstract: A phase-locked loop apparatus (PLL apparatus) and a tuning voltage providing circuit thereof are provided. The PLL apparatus is for receiving an input signal and producing an output signal according to the received input signal. The PLL apparatus includes a voltage-controlled oscillator (VCO), a loop filter and a tuning voltage providing circuit. The VCO receives a control voltage and produces the output signal according to the received control voltage. The loop filter has a resistor-capacitor network and the network receives the control voltage and is coupled to a reference voltage. The tuning voltage providing circuit receives the output signal and the input signal and provides a tuning voltage to the resistor-capacitor network according to the input signal and the output signal.