Patents by Inventor Hsiang-Chih Chen
Hsiang-Chih Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12125457Abstract: A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.Type: GrantFiled: December 1, 2021Date of Patent: October 22, 2024Assignee: NOVATEK Microelectronics Corp.Inventors: Wen-Chi Lin, Li-Wei Chen, Hsiang-Chih Chen, Pao-Yen Lin, Cheng-Wei Sung, Chung-Wen Hung
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Publication number: 20220180838Abstract: A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.Type: ApplicationFiled: December 1, 2021Publication date: June 9, 2022Applicant: NOVATEK Microelectronics Corp.Inventors: Wen-Chi Lin, Li-Wei Chen, Hsiang-Chih Chen, Pao-Yen Lin, Cheng-Wei Sung, Chung-Wen Hung
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Patent number: 8587353Abstract: The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.Type: GrantFiled: November 19, 2012Date of Patent: November 19, 2013Assignee: NOVATEK Microelectronics Corp.Inventors: Tung-Cheng Hsin, Hsiang-Chih Chen
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Publication number: 20130257496Abstract: The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.Type: ApplicationFiled: November 19, 2012Publication date: October 3, 2013Applicant: NOVATEK MICROELECTRONICS CORP.Inventors: Tung-Cheng Hsin, Hsiang-Chih Chen
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Patent number: 8466911Abstract: A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.Type: GrantFiled: November 23, 2009Date of Patent: June 18, 2013Assignee: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Tung-Cheng Hsin
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Patent number: 8294695Abstract: A display driving apparatus and a method thereof are provided. The apparatus includes a memory unit, a compression and decompression unit, a data selection unit, and a display accelerating unit. The memory unit is coupled to the compression and decompression unit and stores only a compressed frame to save memory space in the apparatus. The data selection unit determines whether an error is caused to a frame through data compression and decompression. When the error is greater than a predetermined value, the display accelerating unit turns off an overdriving process upon the pixels to avoid image distortion. The data selection unit also determines whether the frames are static or dynamic in order to determine whether to turn on the overdriving process.Type: GrantFiled: March 26, 2008Date of Patent: October 23, 2012Assignee: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Jui-Lin Lo, Don-Chen Hsin
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Publication number: 20110050681Abstract: A low voltage differential signal (LVDS) output stage including a display signal digital circuit, a data parallel-to-serial (P2S) circuit and a transmitting circuit is provided. The display signal digital circuit generates a display signal and a display clock signal synchronous to each other according to a first frequency multiplication clock signal. The data P2S circuit samples the display signal according to a second frequency multiplication clock signal, so as to generate a serial data signal and a serial clock signal. The first frequency multiplication clock signal and the second frequency multiplication clock signal have a relationship of frequency multiplication. The data P2S circuit includes an adjustment structure for adjusting the serial clock signal according to the display clock signal and the second frequency multiplication clock signal, and controlling a transmitting time of the serial data signal transmitted according to a clock of the second frequency multiplication clock signal.Type: ApplicationFiled: November 23, 2009Publication date: March 3, 2011Applicant: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Tung-Cheng Hsin
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Patent number: 7772893Abstract: A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved.Type: GrantFiled: June 30, 2008Date of Patent: August 10, 2010Assignee: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Don-Chen Hsin
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Publication number: 20090021499Abstract: A display driving apparatus and a method thereof are provided. The apparatus includes a memory unit, a compression and decompression unit, a data selection unit, and a display accelerating unit. The memory unit is coupled to the compression and decompression unit and stores only a compressed frame to save memory space in the apparatus. The data selection unit determines whether an error is caused to a frame through data compression and decompression. When the error is greater than a predetermined value, the display accelerating unit turns off an overdriving process upon the pixels to avoid image distortion. The data selection unit also determines whether the frames are static or dynamic in order to determine whether to turn on the overdriving process.Type: ApplicationFiled: March 26, 2008Publication date: January 22, 2009Applicant: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Jui-Lin Lo, Don-Chen Hsin
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Publication number: 20090015296Abstract: A digital frequency synthesizer and a method thereof are provided. In the digital frequency synthesizer, a plurality of multiphase signals (MPSs) is generated by a phase delay locked loop array, and a transition reference values is generated by a programmable transition value generator. An operation result obtained according to an input signal and an accumulated value is compared with the transition reference values to generate a phase selection control signal. A phase signal is selected among the MPSs according to the phase selection control signal. After that, a sampling control is performed to the selected phase signal to generate a synthetic signal. The digital frequency synthesizer and the method thereof are flexible and are easy to produce tiny analytic phase, thus, not only fine tuning phases is added but also the resolution of the synthetic signal is improved.Type: ApplicationFiled: June 30, 2008Publication date: January 15, 2009Applicant: Novatek Microelectronics Corp.Inventors: Hsiang-Chih Chen, Don-Chen Hsin
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Publication number: 20080272994Abstract: An apparatus for controlling an LCD is provided. The apparatus includes a memory, an image scaler circuit, a liquid crystal accelerating circuit, an image stretcher circuit, and an interface signal transmitting circuit. A first frame data is stored in the memory. The image scaler circuit receives and shrinks a second frame data. The liquid crystal accelerating circuit is coupled to the image scaler circuit, the memory, and the image stretcher circuit for comparing the first and the second frame data and adjusting pixels of the second frame data. The apparatus refreshes the first frame data stored in the memory with the second frame data. The image stretcher circuit enlarges the adjusted second frame data, and transmits an interface signal to a liquid crystal panel module through the interface signal transmitting circuit. The present invention drives the liquid crystal panel module to achieve the output maximum resolution with minimum required memory.Type: ApplicationFiled: July 23, 2007Publication date: November 6, 2008Applicant: NOVATEK MICROELECTRONICS CORP.Inventors: Hsiang-Chih Chen, Tsung-Hsing Hu