Patents by Inventor Hsiang-Fu Chen
Hsiang-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12162749Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: GrantFiled: August 9, 2023Date of Patent: December 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kang-Yi Lien, I-Hsuan Chiu, Yi-Chieh Huang, Chia-Ming Hung, Kuan-Chi Tsai, Hsiang-Fu Chen
-
Publication number: 20240395897Abstract: A method of manufacturing a semiconductor device includes forming a conductive layer over a first substrate, forming at least one circuit element at least partially from a semiconductor material of a second substrate, bonding the first substrate to the second substrate, etching a through via extending through the second substrate to partially expose the conductive layer, depositing at least one conductive material in the through via to form a conductive through via electrically coupled to the conductive layer and over the second substrate to form a first contact structure electrically coupling the conductive through via to the at least one circuit element. The at least one circuit element includes at least one of a Schottky diode, a capacitor, or a resistor.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Chia-Ming HUNG, I-Hsuan CHIU, Hsiang-Fu CHEN, Kang-Yi LIEN, Chu-Heng CHEN
-
Patent number: 12153868Abstract: An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.Type: GrantFiled: December 9, 2022Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chih Hsieh, Chun-Fu Chen, Ting-Wei Chiang, Hui-Zhong Zhuang, Hsiang-Jen Tseng
-
Publication number: 20240383005Abstract: A semiconductor device and method of manufacturing the device that includes a capacitive micromachined ultrasonic transducer (CMUT). The CMUT includes an integrated circuit substrate, and a sensing electrode positioned on the integrated substrate. The sensing electrode includes a sidewall that forms a wall of an isolation trench adjacent to the sensing electrode, and is patterned before covering dielectric layers are deposited. After patterning of the sensing electrode, one or more dielectric layers are patterned, with one dielectric layer patterned on the sensing electrode and sidewall, and which has a thickness corresponding to the surface roughness of the sensing electrode. The CMUT further includes a membrane positioned above the sensing electrode forming a cavity therein.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Wei-Tung Huang, Hsiang-Fu Chen
-
Publication number: 20240375943Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
-
Publication number: 20240304580Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.Type: ApplicationFiled: May 14, 2024Publication date: September 12, 2024Inventors: WEN-CHUAN TAI, FAN HU, HSIANG-FU CHEN, LI-CHUN PENG
-
Patent number: 12015001Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.Type: GrantFiled: March 15, 2022Date of Patent: June 18, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Chuan Tai, Fan Hu, Hsiang-Fu Chen, Li-Chun Peng
-
Publication number: 20240038597Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.Type: ApplicationFiled: July 28, 2022Publication date: February 1, 2024Inventors: FAN HU, WEN-CHUAN TAI, HSIANG-FU CHEN, I-CHIEH HUANG, TZU-CHIEH WEI, KANG-YI LIEN
-
Patent number: 11851323Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition.Type: GrantFiled: June 22, 2020Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
-
Publication number: 20230406695Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A first cavity and a second cavity are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a first movable membrane overlying the first cavity and a second movable membrane overlying the second cavity. A first functional structure overlies the first movable membrane, where the first functional structure comprises a first material having a first chemical composition.Type: ApplicationFiled: August 4, 2023Publication date: December 21, 2023Inventors: Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
-
Publication number: 20230399226Abstract: The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Fan Hu, Wen-Chuan Tai, Li-Chun Peng, Hsiang-Fu Chen, Ching-Kai Shen, Hung-Wei Liang, Jung-Kuo Tu
-
Patent number: 11834332Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: GrantFiled: February 14, 2022Date of Patent: December 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu
-
Patent number: 11834325Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.Type: GrantFiled: June 15, 2022Date of Patent: December 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Publication number: 20230382723Abstract: A semiconductor device and method of manufacturing the device that includes a growth die and a dummy die. The method includes patterning, on an integrated circuit wafer, at one least growth die, and patterning at least one dummy die that is positioned on at least a portion of a circumference of the integrated circuit wafer. The patterned growth and dummy dies are etched on the wafer. A bond wave is initiated at a starting point on the integrated circuit wafer. The starting point is positioned on an edge of the integrated circuit wafer opposite the portion on which the at least one dummy die is patterned. Upon application of pressure at the starting point, a uniform bond wave propagates across the wafers, bonding the two wafers together.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Kang-Yi Lien, I-Hsuan Chiu, Yi-Chieh Huang, Chia-Ming Hung, Kuan-Chi Tsai, Hsiang-Fu Chen
-
Publication number: 20230386948Abstract: A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: You-Ru Lin, Sheng Kai Yeh, Jen-Yuan Chang, Chi-Yuan Shih, Chia-Ming Hung, Hsiang-Fu Chen, Shih-Fen Huang
-
Publication number: 20230382724Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.Type: ApplicationFiled: May 26, 2022Publication date: November 30, 2023Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu, Fan Hu
-
Publication number: 20230373780Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity.Type: ApplicationFiled: August 7, 2023Publication date: November 23, 2023Inventors: Fan Hu, Chun-Ren Cheng, Hsiang-Fu Chen, Wen-Chuan Tai
-
Publication number: 20230331546Abstract: A MEMS package is provided. The MEMS package includes a metallization layer, a planarization structure, a MEMS device structure, a cap structure and a pressure adjustment element. The planarization structure has an inner sidewall defining a first cavity exposing the metallization layer. The MEMS device structure is bonded to the planarization structure. The MEMS device structure includes a movable element over the first cavity. The cap structure is bonded to the MEMS device structure and has an inner sidewall defining a second cavity facing the movable element. The pressure adjustment element is disposed in the second cavity.Type: ApplicationFiled: April 19, 2022Publication date: October 19, 2023Inventors: FAN HU, WEN-CHUAN TAI, LI-CHUN PENG, HSIANG-FU CHEN
-
Publication number: 20230299028Abstract: A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.Type: ApplicationFiled: March 15, 2022Publication date: September 21, 2023Inventors: WEN-CHUAN TAI, FAN HU, HSIANG-FU CHEN, LI-CHUN PENG
-
Publication number: 20230278073Abstract: A semiconductor device and method of manufacturing the same that utilizes dielectric pedestals on a sensing electrode. The semiconductor device includes a one or more membranes and an integrated circuit substrate. The integrated circuit substrate includes one or more conductive components disposed within a first dielectric layer on the substrate, with the conductive components interconnected with respective integrated circuit components. The substrate further includes one or more sensing electrodes electrically coupled to the conductive components, and one or more dielectric pedestals positioned within a landing area of the sensing electrode. In addition, the semiconductor device includes at least one cavity that is formed by the membrane positioned over the sensing electrode.Type: ApplicationFiled: March 7, 2022Publication date: September 7, 2023Inventors: Kang-Yi Lien, Kuan-Chi Tsai, Yi-Chieh Huang, Hsiang-Fu Chen, Chia-Ming Hung, I-Hsuan Chiu