Patents by Inventor Hsiang-Hsiung Yu
Hsiang-Hsiung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9760509Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.Type: GrantFiled: September 9, 2014Date of Patent: September 12, 2017Assignee: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Yuan-Cheng Chang, Wei-Cheng Wu
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Patent number: 9317418Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: June 17, 2014Date of Patent: April 19, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 9310869Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.Type: GrantFiled: August 19, 2014Date of Patent: April 12, 2016Assignee: PHISON ELECTRONICS CORP.Inventors: Chih-Jen Hsu, Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen
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Publication number: 20160018997Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.Type: ApplicationFiled: September 9, 2014Publication date: January 21, 2016Inventors: Hsiang-Hsiung Yu, Yuan-Cheng Chang, Wei-Cheng Wu
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Publication number: 20150323969Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.Type: ApplicationFiled: August 19, 2014Publication date: November 12, 2015Inventors: Chih-Jen Hsu, Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen
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Publication number: 20150305143Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.Type: ApplicationFiled: June 6, 2014Publication date: October 22, 2015Inventors: Yun-Chieh Chen, Shih-Kung Lin, Ta-Chuan Wei, Hsiang-Hsiung Yu
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Patent number: 9155189Abstract: A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.Type: GrantFiled: June 6, 2014Date of Patent: October 6, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Yun-Chieh Chen, Shih-Kung Lin, Ta-Chuan Wei, Hsiang-Hsiung Yu
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Patent number: 9128624Abstract: A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system.Type: GrantFiled: January 22, 2010Date of Patent: September 8, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Hon-Wai Ng, Yi-Hsiang Huang, Shih-Hsien Hsu, Hsiang-Hsiung Yu
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Publication number: 20140297936Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: ApplicationFiled: June 17, 2014Publication date: October 2, 2014Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8837248Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: February 21, 2013Date of Patent: September 16, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8826461Abstract: A method and a system for protecting data, a storage device, and a storage device controller are provided. In the present method, when a host accesses data in the storage device, whether the host performs a play operation or a copy operation on the data is first determined. If the host performs the play operation on the data, the storage device continues to execute the play operation so as to allow the host to access the data. On the other hand, if the host performs the copy operation on the data, the storage device executes an interference procedure so as to prevent or retard the data from being copied into the host.Type: GrantFiled: November 20, 2009Date of Patent: September 2, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yu-Chung Shen, Yun-Chieh Chen
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Patent number: 8806301Abstract: A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip has a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks of the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip.Type: GrantFiled: November 19, 2009Date of Patent: August 12, 2014Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Patent number: 8416621Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: GrantFiled: February 14, 2011Date of Patent: April 9, 2013Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 8255656Abstract: A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation.Type: GrantFiled: June 24, 2010Date of Patent: August 28, 2012Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Chung-Lin Wu, Yi-Hsiang Huang, Yu-Chung Shen
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Patent number: 8230162Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.Type: GrantFiled: February 12, 2010Date of Patent: July 24, 2012Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Publication number: 20120089766Abstract: A non-volatile memory storage apparatus having a connector, an energy storage circuit, a power regulator and supply circuit, a non-volatile memory module, a memory controller and a buffer memory is provided. The power regulator and supply circuit is configured for transforming an output voltage from the energy storage circuit into a first voltage used for the non-volatile memory module and a second voltage used for the memory controller and the buffer memory. The memory controller is configured for writing data stored temporarily in the buffer memory into the non-volatile memory module with a special writing mode when receiving a detecting signal indicating that an input voltage is continuously smaller than a predetermined voltage for a predetermined period or receiving a detecting signal indicating that an inactive status of the connector or receiving a suspend mode signal, a warm reset signal or a hot reset signal from a host system.Type: ApplicationFiled: February 14, 2011Publication date: April 12, 2012Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen, Yu-Chung Shen
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Patent number: 7987316Abstract: The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the first number of sequential bits of the first status in the first data into a second number of sequential bits of second status, and c) programming second data in a portion of the data page where the first status has been decoded to the second status.Type: GrantFiled: February 8, 2008Date of Patent: July 26, 2011Assignee: Phison Electronics Corp.Inventors: Hsiang-Hsiung Yu, Yu-An Chang
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Publication number: 20110145480Abstract: A flash memory storage system including a flash memory chip, a connector, and a controller is provided. The flash memory chip has a plurality of physical blocks. The connector is configured to couple to a host system. The controller is coupled to the flash memory chip and the connector. The controller configures a plurality of logical blocks and maps the logical blocks to a portion of the physical blocks. In addition, the controller identifies rewritable disc commands from the host system and writes data from the host system into the physical blocks mapped to the logical blocks according to the rewritable disc commands. Thereby, a rewritable disc device is simulated by using the flash memory storage system.Type: ApplicationFiled: January 22, 2010Publication date: June 16, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: HON-WAI NG, Yi-Hsiang Huang, Shih-Hsien Hsu, Hsiang-Hsiung Yu
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Publication number: 20110145482Abstract: A block management method for managing blocks of a flash memory storage device is provided. The flash memory storage device includes a flash memory controller. The block management method includes the following steps. At least a part of the blocks is grouped into a first partition and a second partition. Whether an authentication code exists is determined. When the authentication code exists, the blocks belonging to the first partition are provided for a host system to access, so the host system displays the first partition and hides the second partition. An authentication information is received from the host system. Whether the authentication information and the authentication code are identical is authenticated. When the authentication information and the authentication code are identical, the blocks belonging to the second partition are provided for the host system to access, so the host system displays the second partition and hides the first partition.Type: ApplicationFiled: February 12, 2010Publication date: June 16, 2011Applicant: PHISON ELECTRONICS CORP.Inventors: Hsiang-Hsiung Yu, Yi-Hsiang Huang, Chung-Lin Wu, Yu-Chung Shen
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Patent number: 7944666Abstract: A hot plug electronic device with high using safety is provided. The hot plug electronic device includes an operation circuit, a voltage regulator and an over-thermal protection device. The operation circuit is used for communicating with an external host. The voltage regulator is coupled to the operation circuit for supplying power to the operation circuit. The over-thermal protection device is coupled to the voltage regulator for sensing the present temperature of the hot plug electronic device, and accordingly controlling the voltage regulator to normally supply/stop supplying the power to the operation circuit.Type: GrantFiled: September 15, 2008Date of Patent: May 17, 2011Assignee: Phison Electronics Corp.Inventors: Yu-Tong Lin, Hsiang-Hsiung Yu