Abstract: A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.

Abstract: A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels.

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

Abstract: A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.

Abstract: A chip package including a semiconductor die, an insulating encapsulant, and a first redistribution layer is provided. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is provided over the semiconductor die and the encapsulant and includes a first redistribution portion and a second redistribution portion in contact with the first redistribution portion. The first redistribution portion is between the second redistribution portion and the semiconductor die. The first redistribution portion includes a first dielectric portion and a plurality of first conductive features embedded in the first dielectric portion. The plurality of first conductive features electrically connects the semiconductor die to the second redistribution portion. The second redistribution portion includes a second dielectric portion and a plurality of second conductive features embedded in the second dielectric portion and connected to the first conductive features.

Abstract: A display device is provided. The display device includes a panel, a memory, and a controller. The panel includes multiple pixels. The memory includes a first section and a second section. The memory stores an aging record table. Multiple brightness attenuation values recorded in the aging table are respectively divided into multiple first portion attenuation values and multiple second portion attenuation values. The first section stores the first portion attenuation values. The second section stores the second portion attenuation values. The controller includes an update circuit and a compensation circuit. The controller is coupled to the panel and the memory. The update circuit receives gray values displayed by the pixels to update the aging table. The compensation circuit reads the first portion attenuation values from the first section so as to perform an aging compensation on the pixels.

Abstract: A method of manufacturing a semiconductor structure includes receiving a die comprising a top surface and a sacrificial layer covering the top surface; disposing the die on a substrate; disposing a molding surrounding the die; removing a portion of the molding to expose a sidewall of the sacrificial layer, wherein a top surface of the molding is at a level substantially same as the top surface of the die; and removing the sacrificial layer from the die.

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A method for treating a micro electro-mechanical system (MEMS) component is disclosed. In one example, the method includes the steps of providing a first wafer, treating the first wafer to form cavities and at least an oxide layer on a top surface of the first wafer using a first chemical vapor deposition (CVD) process, providing a second wafer, bonding the second wafer on a top surface of the at least one oxide layer, treating the second wafer to form a first plurality of structures, depositing a layer of Self-Assembling Monolayer (SAM) to a surface of the MEMS component using a second CVD process.

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.

Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a polymer layer and a redistribution layer. The encapsulant laterally encapsulates the die. The polymer layer is on the encapsulant and the die. The polymer layer includes an extending portion having a bottom surface lower than a top surface of the die. The redistribution layer penetrates through the polymer layer to connect to the die.

Abstract: A method of manufacturing a semiconductor device includes forming a polymer mixture over a substrate, curing the polymer mixture to form a polymer material, and patterning the polymer material. The polymer mixture includes a polymer precursor, a photosensitizer, a cross-linker, and a solvent. The polymer precursor may be a polyamic acid ester. The cross-linker may be tetraethylene glycol dimethacrylate. The photosensitizer includes 4-phenyl-2-(piperazin-1-yl)thiazole. The mixture may further include an additive.

Abstract: A method includes encapsulating a device die in an encapsulating material, forming a first dielectric layer over the device die and the encapsulating material, forming first redistribution lines extending into the first dielectric layer to electrically couple to the device die, forming an alignment mark over the first dielectric layer, wherein the alignment mark includes a plurality of elongated strips, forming a second dielectric layer over the first redistribution lines and the alignment mark, and forming second redistribution lines extending into the second dielectric layer to electrically couple to the first redistribution lines. The second redistribution lines are formed using the alignment mark for alignment.

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure.

Abstract: A package structure includes a semiconductor die, an insulating encapsulation, a first redistribution circuit structure and a surface-modifying film. The semiconductor die has conductive terminals. The insulating encapsulation laterally encapsulates the semiconductor die and exposes the conductive terminals. The first redistribution circuit structure is located over the insulating encapsulation and electrically connected to the semiconductor die. The surface-modifying film is located on the insulating encapsulation and has a plurality of openings exposing edges of the conductive terminals, wherein the surface-modifying film separates the first redistribution circuit structure from the insulating encapsulation.

Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.