Patents by Inventor HSIANG-HUA HSU

HSIANG-HUA HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088124
    Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
  • Patent number: 11195905
    Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiang-Hua Hsu, Liang-An Huang, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Chih-Chung Wang, Kuang-Hsiu Chen, Ke-Feng Lin, Yan-Huei Li, Kai-Ting Hu
  • Publication number: 20200266267
    Abstract: A metal-oxide-semiconductor (MOS) transistor includes a substrate. The substrate has a plurality of trenches extending along a first direction and located on a top portion of the substrate. A gate structure line is located on the substrate and extends along a second direction intersecting with the first direction and crossing over the trenches. A first doped line is located in the substrate, located at a first side of the gate structure line, and crosses over the trenches. A second doped line is located in the substrate, located at a second side of the gate structure line, and crosses over the trenches.
    Type: Application
    Filed: March 19, 2019
    Publication date: August 20, 2020
    Applicant: United Microelectronics Corp.
    Inventors: HSIANG-HUA HSU, Liang-An Huang, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Chih-Chung Wang, Kuang-Hsiu Chen, Ke-Feng Lin, Yan-Huei Li, Kai-Ting Hu