Abstract: The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.

Abstract: The present invention provides a memory device and a test method thereof that can detect a coupling fault between two memory arrays. The memory device includes a memory array unit and a test module. The memory array unit includes a value memory array and a mask memory array. The test module is coupled to the memory array unit for generating a test pattern signal that is based on a test rule and that is provided to the memory array unit for performing testing on the memory array unit. The test rule includes a number (M) of first test segments for testing the value memory array and a number (N) of second test segments for testing the mask memory array. The first test segments and the second test segments are interleaved in the test rule.

Abstract: The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.