Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract: A method for controlling device feature sizes produced by polishing operations such as chemical mechanical polishing (CMP) is provided. The method includes instituting process controls to control the processing operations used in combination to produce features of a metal layer with a desired thickness, based on the thickness of the previous metal layer or layers. A target thickness for first and second metal layers is established. After the first metal layer is produced and the difference between the first metal target thickness and the actual first metal thickness is determined, the target thickness for the second metal features is adjusted. Once the target thickness for the second metal features is adjusted, each of the processing operations used to produce the second metal layer is controlled in combination to produce the second metal features with the adjusted target thickness.

Abstract: A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.

Abstract: A method for controlling device feature sizes produced by polishing operations such as chemical mechanical polishing (CMP) is provided. The method includes instituting process controls to control the processing operations used in combination to produce features of a metal layer with a desired thickness, based on the thickness of the previous metal layer or layers. A target thickness for first and second metal layers is established. After the first metal layer is produced and the difference between the first metal target thickness and the actual first metal thickness is determined, the target thickness for the second metal features is adjusted. Once the target thickness for the second metal features is adjusted, each of the processing operations used to produce the second metal layer is controlled in combination to produce the second metal features with the adjusted target thickness.