Patents by Inventor Hsiang-Hung Peng

Hsiang-Hung Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12224108
    Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: February 11, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Feng-Lung Chien, Tsang-Feng Wu, Yuan Han, Tzu-Chieh Kao, Chien-Hung Lin, Kuang-Lun Lee, Hsiang-Hui Hsu, Shu-Yi Tsui, Kuo-Jui Lee, Kun-Ying Lee, Mao-Chun Chen, Tai-Hsien Yu, Wei-Yu Chen, Yi-Ju Li, Kuei-Yuan Chang, Wei-Chun Li, Ni-Ni Lai, Sheng-Hao Luo, Heng-Sheng Peng, Yueh-Hui Kuan, Hsiu-Chen Lin, Yan-Bing Zhou, Chris T. Burket
  • Publication number: 20240407273
    Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.
    Type: Application
    Filed: July 6, 2023
    Publication date: December 5, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Hsiang-Hung Peng, Yu-Huan Yeh, Chuan-Fu Wang
  • Publication number: 20240188306
    Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 6, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang, Hsiang-Hung Peng
  • Patent number: 11296036
    Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: April 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Publication number: 20200365521
    Abstract: A mark pattern includes unit cells immediately adjacent to each other and arranged in a form of dot matrix to form a register mark or an identification code, wherein each unit cell has configuration identical to functional devices of pMOS and nMOS, and each unit cell includes a first active region, a second active region isolated from the first active region, and first gate structures extending along a first direction and are arranged along a second direction perpendicular to the first direction, and the first gate structures straddling the first active region and the second active region, contact structures disposed between the first gate structures on the first active region and the second active region, and via structures disposed on the contact structures and two opposite ends of the first gate structures.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Patent number: 10777508
    Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Patent number: 10199374
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Publication number: 20180166441
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Application
    Filed: November 28, 2017
    Publication date: June 14, 2018
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Publication number: 20180130753
    Abstract: A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.
    Type: Application
    Filed: November 9, 2016
    Publication date: May 10, 2018
    Inventors: Chih-Kai Kang, Sheng-Yuan Hsueh, Yi-Chung Sheng, Kuo-Yu Liao, Shu-Hung Yu, Hung-Hsu Lin, Hsiang-Hung Peng
  • Patent number: 9865593
    Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Hsiang-Hung Peng, Wei-Hao Huang, Ching-Wen Hung, Chih-Sen Huang
  • Patent number: 7872852
    Abstract: A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: January 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tsuoe-Hsiang Liao, Huo-Tieh Lu, Chih-Chien Liu, Hsiang-Hung Peng, Yu-Fang Chien
  • Publication number: 20090201625
    Abstract: A three-dimensional conductive structure has a first electrode and a second electrode of a capacitor structure, and thereby defines a capacitor space. At least a signal line is further included in the capacitor space where both the first electrode and the second electrode can cross and detour round the signal line. Therefore, the signal line can go directly through the capacitor space for transferring various signals without making a detour to avoid the whole capacitor structure.
    Type: Application
    Filed: February 12, 2008
    Publication date: August 13, 2009
    Inventors: Tsuoe-Hsiang Liao, Huo-Tieh Lu, Chih-Chien Liu, Hsiang-Hung Peng, Yu-Fang Chien
  • Patent number: 5571322
    Abstract: A pencil marking device for clipped cloth includes a fixing base, a pencil pedestal, a driving pedestal, a driving source, and at least two sensors, in which the fixing base is fixed on the automatic marking machinery, and the pencil pedestal is connected in it. The tooth ring is formed on the outside of the pencil pedestal. The driving pedestal is installed on one side of the fixing pedestal and is engaged with the tooth ring of the pencil pedestal through an active gear rack for driving the pencil pedestal to rotate at a fix point. The active gear rack is connected with the driving source by an U shape connection and driven to move horizontally by the driving source. The sensors are installed on the ends of the driving pedestal respectively for sensing the moving range of the active gear rack. The range of the horizontal movement of the active gear rack is restricted for driving the pencil in the pencil pedestal to rotate and mark at a fix position, then an automatic pencil marking device is constructed.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: November 5, 1996
    Assignee: China Textile Institute
    Inventors: Shin-Chuan Yao, Yun-Kuang Lin, Hsiang-Hung Peng