Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first device tier including a first semiconductor substrate having a first plurality of devices. A second semiconductor substrate is formed over the first device tier. A first conductive layer is formed within the second semiconductor substrate, and a second conductive layer is formed within the second semiconductor substrate and over the first conductive layer. The first conductive layer and the second conductive layer have different patterns as viewed from a top-view. A second plurality of devices are formed on the second semiconductor substrate. The first and second conductive layers are configured to electrically couple the first plurality of devices and the second plurality of devices.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure. A second active semiconductor region is disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction. A first conductive structure is disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: An integrated circuit designing system includes a non-transitory storage medium that is encoded with first and second sets of standard cell layouts that are configured for performing a selected function and which correspond to a specific manufacturing process. The manufacturing process is characterized by a nominal minimum pitch (T) for metal lines with each of the standard cell layouts being characterized by a cell height (H) that is a non-integral multiple of the nominal minimum pitch. The system also includes a hardware processor coupled to the storage medium for executing a set of instructions for generating an integrated circuit layout utilizing a combination of the first and second set of standard cell layouts and the nominal minimum pitch. The first and second sets of standard layouts are related in that each of the second set of standard cell layouts corresponds to a transformed version of a corresponding standard cell layout from the first set of standard cell layouts.

Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method is performed by forming a gate structure over a substrate, and selectively implanting the substrate according to the gate structure to form first and second source/drain regions on opposing sides of the gate structure. A first MEOL structure is formed on the first source/drain region and a second MEOL structure is formed on the second source/drain region. The first MEOL structure has a bottommost surface that extends in a first direction from directly over the first source/drain region to laterally past an outermost edge of the first source/drain region. A conductive structure is formed to contact the first MEOL structure and the second MEOL structure. The conductive structure laterally extends from directly over the first MEOL structure to directly over the second MEOL structure along a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of the first source/drain regions corresponds to a first source/drain terminal of a respective one of the first and second transistors. Each of the second source/drain regions corresponds to a second source/drain terminal of a respective one of the first and second transistors. The cell includes a first voltage rail, a pair of second voltage rails, and a cell circuit. The first voltage rail is coupled to the first source/drain regions. Each of the second voltage rails is coupled to a respective one of the second source/drain regions and is configured to be coupled to the first voltage rail. The cell circuit is coupled to one of the second voltage rails.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. A first active semiconductor region is disposed in a first vertical level of the semiconductor structure. A second active semiconductor region is disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction. A first conductive structure is disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier interconnecting structure disposed within the semiconductor substrate. The inter-tier interconnect structure includes a first connection point at a lower surface of the inter-tier interconnecting structure and a second connection point at an upper surface of the inter-tier interconnecting structure. The first connection point and the second connection point are not vertically aligned. The inter-tier interconnecting structure includes one or more conductive layers extending between the first and second connection points.

Abstract: A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.