Abstract: The invention concerns methods and means for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: An EUV lithography mask including a substrate, a patterned absorber layer including an alloy of rhodium. In some embodiments, the alloy of rhodium includes a group 5, group 6, group 9, group 10, or group 11 transition metal having a specific EUV refractive index and a specific EUV extinction coefficient. The disclosed EUV lithography masks reduce undesirable mask 3D effects.

Abstract: A package structure includes a first layer, a second layer and a third layer. The second layer includes an outer frame, a resonator and a chip. The second layer is arranged between the first layer and the third layer. The outer frame, the first layer and the third layer are constituted a rectangular accommodation portion. The resonator and the chip are located in the rectangular accommodation portion. The chip is located at a side of the resonator, and is electrically connected to the third layer and the resonator through a plurality of conductive components on the chip. A package structure in which the chip is located below the resonator is also provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a metallization layer. The metallization layer is disposed over the substrate. The metallization layer includes a first signal line, a second signal line, and a third signal line, wherein the first signal line, the second signal line, and the third signal line are arranged in a first row between a power rail and a ground rail parallel to the power rail. A first distance between the first signal line and the second signal line is different from a second distance between the second signal line and the third signal line. A method for manufacturing a semiconductor structure is also provided.

Abstract: An electronic device includes a battery module, a battery connector and a controller is provided. The battery connector includes a first connector and a second connector. The first connector is installed on the battery module and includes a first metal component and an enable pin. The first metal component is disposed on a housing of the first connector and is coupled to the enable pin. The second connector includes a second metal component, a detection pin and a ground pin. The second metal component is disposed on a housing of the second connector. The detection pin is coupled to the second metal component. The ground pin is coupled to a ground potential and its position corresponds to the position of the enable pin. The controller determines a connection status of the first connector and the second connector according to an external signal on the detection pin.

Abstract: A measurement module is adapted to be disposed in a target object, including a corner prism space and multiple measurement units. The corner prism space includes two bottom surfaces opposite to each other and multiple side surfaces. The measurement units are disposed on the side surfaces of the corner prism space respectively. Each of the measurement units has a positioning reference axis perpendicular to the corresponding side surface. A number of the measurement units is the same as a number of the side surfaces, and the number of the measurement units is at least five.

Abstract: The present application discloses variants of Pertuzumab. In particular, it discloses: an unpaired cysteine variant comprising Cys23/Cys88 unpaired cysteines in one or both variable light domains of Pertuzumab, an afucosylated variant of Pertuzumab, a low-molecular-weight-species (LMWS) of Pertuzumab, and a high-molecular-weight-species (HMWS) or Pertuzumab. The application further discloses the isolated variants, compositions, pharmaceutical compositions, and articles of manufacture comprising the variants, as well as methods of making and characterizing the variants and compositions thereof.

Abstract: A system for the treatment of oxidizable contaminants in wastewater includes a contaminant treatment vessel and a hydrogen peroxide supply unit. The hydrogen peroxide supply unit includes a hydrogen peroxide transfer line in fluid communication with the contaminant treatment vessel with an air-gap. A wastewater feed stream may also be in fluid communication with the contaminant treatment vessel. A contaminant treatment vessel effluent stream may also be in fluid communication with the contaminant treatment vessel. A method for the treatment of oxidizable contaminants in wastewater includes supplying wastewater to a contaminant treatment vessel, supplying hydrogen peroxide to the contaminant treatment vessel so that the supply is above the maximum filling level of the vessel in an air-gap, and contacting wastewater in the contaminant treatment vessel with hydrogen peroxide.

Abstract: The present disclosure provides a method and a non-transitory computer-readable medium for generating layout based on path labeled with marker. The method includes: generating a first layout, wherein the first layout includes a plurality of paths; labeling a first path in the first layout with a first marker or a second marker; and generating a second layout by performing an optical proximity correction operation to the first layout, wherein a second path in the second layout corresponds to the first path in the first layout, the second path is not corrected during the optical proximity correction operation when the first path is labeled with the first marker, and the second path is corrected during the optical proximity correction operation when the first path is labeled with the second marker.

Abstract: A frequency generating device and an operation method thereof are provided. The frequency generating device includes an oscillator circuit and a processor circuit. The oscillator circuit generates a clock signal and adjust a clock frequency of the clock signal according to a control voltage generated by the processor circuit. The processor circuit calculates a current frequency aging rate value based on a current clock frequency. The processor circuit calculates a control voltage regulation rate value based on the current frequency aging rate value and a control voltage slope, and compensates the control voltage based on the control voltage regulation rate value in the holdover state. Alternatively, the processor circuit calculates a frequency regulation value based on the current frequency aging rate value and an oscillator resolution of the synchronizer, and provides the frequency regulation value to the synchronizer in the holdover state to compensate an output frequency of the synchronizer.

Abstract: The invention concerns methods and means for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: The invention concerns methods for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: The present application discloses variants of Pertuzumab. In particular, it discloses: an unpaired cysteine variant comprising Cys23/Cys88 unpaired cysteines in one or both variable light domains of Pertuzumab, an afucosylated variant of Pertuzumab, a low-molecular-weight-species (LMWS) of Pertuzumab, and a high-molecular-weight-species (HMWS) or Pertuzumab. The application further discloses the isolated variants, compositions, pharmaceutical compositions, and articles of manufacture comprising the variants, as well as methods of making and characterizing the variants and compositions thereof.

Abstract: The invention concerns methods for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A hard mask (HM) layer is formed over a dielectric layer over a substrate. A plurality of mandrels are formed over the HM layer. A spacer layer including a plurality of trenches between the mandrels is formed over the HM layer and the mandrels. A first and a second portion of the trenches is filled by a first and a second block material, respectively. A third portion of the trenches is free from filled by these block materials. At least a first opening is formed in the spacer layer. At least a second opening is formed by removing a portion of the mandrels. The HM layer is etched through the first and the second openings. The dielectric layer is patterned. A plurality of conductive lines are formed in the patterned dielectric layer.

Abstract: A frequency generating device and an operation method thereof are provided. The frequency generating device includes an oscillator circuit and a processor circuit. The oscillator circuit is configured to generate a clock signal and adjust a clock frequency of the clock signal according to a control voltage. The processor circuit is coupled to the oscillator circuit and is configured to generate the control voltage. The processor circuit reads a frequency aging rate value and a control voltage slope of the oscillator circuit from the oscillator circuit, calculates a control voltage regulation rate value corresponding to the frequency aging rate value and the control voltage slope, and compensates the control voltage based on the control voltage regulation rate value. Alternatively, the processor circuit reads the control voltage regulation rate value from the oscillator circuit, and compensates the control voltage based on the control voltage regulation rate value.

Abstract: The invention concerns methods and means for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: The invention concerns methods and means for preventing the reduction of disulfide bonds during the recombinant production of disulfide-containing polypeptides. In particular, the invention concerns the prevention of disulfide bond reduction during harvesting of disulfide-containing polypeptides, including antibodies, from recombinant host cell cultures.

Abstract: A chip-assisted design device and a method for constructing a chip characteristic distribution model. The apparatus includes a database and a processor. The database has a first chip characteristic distribution image data generated based on a wafer fabrication process data of a current process, wherein the first chip characteristic distribution image data represents a gradient distribution of at least one chip characteristic in one of the wafers produced through current fabrication process. The processor is coupled to the database. A second chip characteristic image data generated based on the first chip characteristic image data is used as a reference data for predicting the future wafer fabrication process, and the reference data is provided to the current fabrication process to evaluate or correct the first chip characteristic image.

Abstract: A frequency generating device and an operation method thereof are provided. The frequency generating device includes an oscillator circuit and a processor circuit. The oscillator circuit is configured to generate a clock signal and adjust a clock frequency of the clock signal according to a control voltage. The processor circuit is coupled to the oscillator circuit and is configured to generate the control voltage. The processor circuit reads a frequency aging rate value and a control voltage slope of the oscillator circuit from the oscillator circuit, calculates a control voltage regulation rate value corresponding to the frequency aging rate value and the control voltage slope, and compensates the control voltage based on the control voltage regulation rate value. Alternatively, the processor circuit reads the control voltage regulation rate value from the oscillator circuit, and compensates the control voltage based on the control voltage regulation rate value.