Patents by Inventor Hsiang-Ku Shen

Hsiang-Ku Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250253230
    Abstract: The present disclosure provides a semiconductor structure that includes a substrate having devices formed thereon and an interconnect structure electrically coupling the devices into an integrated circuit; a passivation structure formed on the interconnect structure; and a capacitor embedded in the passivation structure, wherein the capacitor includes first metal-insulator-metal (MIM) stacks inserted in first trenches, and second MIM stacks formed into first pillar structures.
    Type: Application
    Filed: October 4, 2024
    Publication date: August 7, 2025
    Inventors: Tzu-Ting LIU, Hsiang-Ku SHEN, Yi-Shan HSIEH, Chia-Yueh CHOU, Ying-Ju WU, Chen-Chiu HUANG, Dian-Hau CHEN
  • Publication number: 20250234568
    Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-En JENG, Hsiang-Ku SHEN, Cheng-Hao HOU, Chen-Chiu HUANG, Dian-Hau CHEN
  • Patent number: 12356633
    Abstract: A semiconductor device includes a substrate, a gate structure, a source region and a drain region, a conductive via and an isolation structure. The gate structure is disposed over the substrate. The source region and the drain region aside the gate structure. The conductive via is disposed in the substrate. The isolation structure is disposed in the substrate, wherein a first surface of the isolation structure is substantially flush with a first surface of the conductive via.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Ku Shen, Liang-Wei Wang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20250192026
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.
    Type: Application
    Filed: February 17, 2025
    Publication date: June 12, 2025
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12327785
    Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 10, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Wen-Chiung Tu, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20250185262
    Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.
    Type: Application
    Filed: February 3, 2025
    Publication date: June 5, 2025
    Inventors: Wen-Chiung Tu, Hsiang-Ku Shen, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Patent number: 12300640
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
  • Publication number: 20250149482
    Abstract: In an embodiment, a method includes forming active devices over a semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line.
    Type: Application
    Filed: February 26, 2024
    Publication date: May 8, 2025
    Inventors: Yi-Shan Hsieh, Chen-Chiu Huang, Yu-Bey Wu, Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250151630
    Abstract: Methods and devices are provided that include a magnetic tunneling junction (MTJ) element. A first spacer layer abuts sidewalls of the MTJ element. The first spacer layer has a low-dielectric constant (low-k) oxide composition. A second spacer layer is disposed on the first spacer layer and has a low-k nitride composition.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Inventors: Hsiang-Ku SHEN, Dian-Hau CHEN
  • Publication number: 20250149427
    Abstract: In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.
    Type: Application
    Filed: February 6, 2024
    Publication date: May 8, 2025
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Chen-Chiu Huang, Yu-Bey Wu, Dian-Hau Chen
  • Publication number: 20250143189
    Abstract: A first metal layer extends across memory and logic device regions of a semiconductor structure. A dielectric barrier layer is disposed over the first metal layer. A first dielectric layer is disposed over the dielectric barrier layer in the memory device region and not in the logic device region. Multiple magnetic tunneling junction (MTJ) devices are disposed in the memory device region. A second dielectric layer is disposed in the memory device region and not in the logic device region. The second dielectric layer is disposed over the first dielectric layer and the MTJ devices. An extreme low-k dielectric layer is disposed over the dielectric barrier layer in the logic device region. A conductive feature in the logic device region penetrates the extreme low-k dielectric layer and the dielectric barrier layer to electrically connect to the first metal layer.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20250140687
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming an interconnect structure over a substrate. The method further includes forming a passivation layer over the interconnect structure. The method further includes forming a conductive structure over the passivation layer, wherein the conductive structure includes a surrounding portion over the passivation layer, and a concave portion surrounded by the surrounding portion. A height of the surrounding portion is greater than a height of the concave portion calculated from a top surface of the passivation layer. The method further includes forming a liner over the conductive structure, wherein an oxygen-to-silicon ratio of the liner is lower than about 1.8.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling CHANG, Chi-Hao CHANG, Hsiang-Ku SHEN, Dian-Hau CHEN
  • Publication number: 20250118654
    Abstract: A passivation layer is formed over an interconnect structure. An opening is etched at least partially through the passivation layer. A first conductive layer is deposited over the passivation layer. The first conductive layer partially fills the opening. An insulator layer is deposited over the first conductive layer. The insulator layer partially fills the opening. A second conductive layer is deposited over the insulator layer. The second conductive layer completely fills the opening. A first conductive structure is formed that is electrically coupled to the first conductive layer. A second conductive structure is formed that is electrically coupled to the second conductive layer.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Inventors: Ying-Ju Wu, Tzu-Ting Liu, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20250118683
    Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a substrate having a circuit region and a chip corner region; IC devices formed on the substrate within the circuit region; a passivation layer formed over the IC devices; and a polyimide layer formed over the passivation layer, wherein the passivation layer and the polyimide layer include a stress-release pattern formed in the chip corner region.
    Type: Application
    Filed: February 16, 2024
    Publication date: April 10, 2025
    Inventors: Wen-Ling CHANG, Wen-Chiung TU, Chen-Chiu HUANG, Hsiu-Wen HSUEH, Hsiang-Ku SHEN, Dian-Hau CHEN, Po-Hsiang HUANG, Ke-Rong HU, Cheng-Nan LIN
  • Patent number: 12266681
    Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-En Jeng, Hsiang-Ku Shen, Cheng-Hao Hou, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20250089277
    Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing forming a first metal-insulator-metal (MIM) capacitor over a substrate and forming a second MIM capacitor over the first MIM capacitor. The forming of the first MIM capacitor includes forming a first conductor plate over a substrate, the first conductor plate comprising a first metal element, conformally depositing a first dielectric layer on the first conductor plate, the first dielectric layer comprising the first metal element, forming a first high-K dielectric layer on the first dielectric layer, conformally depositing a second dielectric layer on the first high-K dielectric layer, the second dielectric layer comprising a second metal element, and forming a second conductor plate over the second dielectric layer, the second conductor plate comprises the second metal element.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 13, 2025
    Inventors: Chia-Yueh Chou, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen, Cheng-Hao Hou, Kun-Yu Lee, Ming-Ho Lin, Alvin Universe Tang, Chun-Hsiu Chiang
  • Patent number: 12243909
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.
    Type: Grant
    Filed: December 22, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12230566
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: February 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
  • Patent number: 12218186
    Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack that includes a plurality of conductor plate layers interleaved by a plurality of insulator layers. The MIM stack includes a first region and a second region and the first region and the second region overlaps in a third region. The MIM stack further includes a first via passing through the first region and electrically coupled to a first subset of the plurality of conductor plate layers, a second via passing through the second region and electrically coupled to a second subset of the plurality of conductor plate layers, and a ground via passing through the third region and electrically coupled to a third subset of the plurality of conductor plate layers.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chiung Tu, Hsiang-Ku Shen, Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20250038105
    Abstract: The present disclosure provides a semiconductor structure that includes a substrate having a circuit region and a seal ring region around the circuit region. The seal ring region includes a multi-layer interconnect to form a seal ring structure. And a redistribution layer is formed over the seal ring structure. The redistribution layer is formed on the edges of the seal ring region, and excluded from corner regions of the seal ring.
    Type: Application
    Filed: November 17, 2023
    Publication date: January 30, 2025
    Inventors: Wen-Chiung Tu, Hsiang-Ku Shen, Chen-Chiu Huang, Dian-Hau Chen, Shu Fang Chen