Patents by Inventor Hsiang-Lin Chen

Hsiang-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11600737
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20230069164
    Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, a second substrate including a second front side and a second back side, a third substrate including a third front side and a third back side, a first interconnect structure, and a second interconnect structure. The first substrate includes a layer and a first light-sensing element in the layer. The layer includes a first semiconductor material, and the first light-sensing element includes a second semiconductor material. The second substrate is bonded to the first substrate with the second front side facing the first back side. The third substrate is bonded to the first substrate with the third front side facing the first front side. The first interconnect structure and the second interconnect structure are disposed between the first front side and the third front side.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: JHY-JYI SZE, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Patent number: 11508817
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20220367638
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20220310871
    Abstract: A method of manufacturing a semiconductor structure includes: forming a light-absorption layer in a substrate; forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the light-absorption layer adjacent to the first doped region; depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region; forming a first silicide layer in the opening on the second doped region; depositing a barrier layer over the first doped region; and annealing the barrier layer to form a second silicide layer on the first doped region.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 29, 2022
    Inventors: YI-SHIN CHU, HSIANG-LIN CHEN, YIN-KAI LIAO, SIN-YI JIANG, KUAN-CHIEH HUANG
  • Publication number: 20220302336
    Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair doped region pair in the germanium layer is configured as an e-lens of the germanium-based sensor.
    Type: Application
    Filed: July 23, 2021
    Publication date: September 22, 2022
    Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
  • Publication number: 20220271080
    Abstract: The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Inventors: JHY-JYI SZE, SIN-YI JIANG, YI-SHIN CHU, YIN-KAI LIAO, HSIANG-LIN CHEN, KUAN-CHIEH HUANG, JUNG-I LIN
  • Publication number: 20220102410
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 31, 2022
    Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
  • Publication number: 20220037552
    Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.
    Type: Application
    Filed: June 2, 2021
    Publication date: February 3, 2022
    Inventors: Yin-Kai LIAO, Jen-Cheng LIU, Kuan-Chieh HUANG, Chih-Ming HUNG, Yi-Shin CHU, Hsiang-Lin CHEN, Sin-Yi JIANG
  • Publication number: 20210376086
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.
    Type: Application
    Filed: September 29, 2020
    Publication date: December 2, 2021
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Patent number: 9099530
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 4, 2015
    Assignee: Taiwan Semiconductor Manufacturing Compnay, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Patent number: 9070688
    Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m?1.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 30, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhun Hua Chen, Yu-Lung Tung, Chi-Tien Chen, Hua-Tai Lin, Hsiang-Lin Chen, Hung-Chang Hsieh, Yi-Fan Chen
  • Publication number: 20140242794
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Patent number: 8728332
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Publication number: 20140035149
    Abstract: A semiconductor device includes a semiconductor substrate, a first active region in the semiconductor substrate, and a second active region in the semiconductor substrate. The semiconductor device further includes a first conductive line over the semiconductor substrate electrically connected to the first active region and having a first end face adjacent to the second active region, and the first end face having an image log slope of greater than 15 ?m-1.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhun Hua CHEN, Yu-Lung TUNG, Chi-Tien CHEN, Hua-Tai LIN, Hsiang-Lin CHEN, Hung-Chang HSIEH, Yi-Fan CHEN
  • Patent number: 8642451
    Abstract: A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: February 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ming Chang, Chang-Ta Yang, Huai-Ying Huang, Ping-Wei Wang, Hsiang-Lin Chen
  • Patent number: 8580637
    Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhun Hua Chen, Yu-Lung Tung, Chi-Tien Chen, Hua-Tai Lin, Hsiang-Lin Chen, Hung Chang Hsieh, Yi-Fan Chen
  • Publication number: 20130295769
    Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 7, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yi Lin, Jiing-Feng Yang, Tzu-Hao Huang, Chih-Hao Hsieh, Dian-Hau Chen, Hsiang-Lin Chen, Ko-Bin Kao, Yung-Shih Cheng
  • Publication number: 20130154100
    Abstract: A pattern on a semiconductor substrate is formed using two separate etching processes. The first etching process removes a portion of an intermediate layer above an active region of the substrate. The second etching process exposes a portion of the active region of the substrate. A semiconductor device formed using the patterning method has a decreased mask error enhancement factor and increased critical dimension uniformity than the prior art.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jhun Hua CHEN, Yu-Lung TUNG, Chi-Tien CHEN, Hua-Tai LIN, Hsiang-Lin CHEN, Hung-Chang HSIEH, Yi-Fan CHEN
  • Publication number: 20120108036
    Abstract: A method includes forming an SRAM cell including a first and a second pull-up transistor and a first and a second pull-down transistor. The step of forming the SRAM cell includes forming a first and a second active region of the first and the second pull-up transistors using a first lithography mask, and forming a third and a fourth active region of the first and the second pull-down transistors using a second lithography mask.
    Type: Application
    Filed: November 1, 2010
    Publication date: May 3, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Ming Chang, Chang-Ta Yang, Huai-Ying Huang, Ping-Wei Wang, Hsiang-Lin Chen