Patents by Inventor Hsiang Lung

Hsiang Lung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153815
    Abstract: The application discloses a semiconductor memory device and a data storage method. When determining that an input data conforms to a target format, an input data vector is generated based on the input data. When determining that the input data is similar to a stored data in a target block of the memory array, the input data is written to a blank target memory page of the target block of the memory array.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: November 26, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Cheng Su, Chih-Hsiang Yang, Hsiang-Lan Lung
  • Publication number: 20240387644
    Abstract: Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 21, 2024
    Inventors: Hsin-Han TSAI, Hsiang-Ju LIAO, Yi-Lun LI, Cheng-Lung HUNG, Weng CHANG, Chi On CHUI, Jo-Chun HUNG, Chih-Wei LEE, Chia-Wei CHEN
  • Publication number: 20240389353
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Sheng TANG, Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240371797
    Abstract: A semiconductor structure includes a core layer; a passive component disposed within the core layer; and a first redistribution layer disposed over the core layer, wherein the first redistribution layer includes a first interconnect, a second interconnect, and a third interconnect disposed between and electrically isolated from the first interconnect and the second interconnect. The third interconnect is electrically connected to the passive component, and at least one of the first interconnect and the second interconnect is electrically isolated from the passive component. A method of manufacturing the semiconductor structure includes providing a first bias between the first interconnect and the second interconnect, providing a second bias to the passive component through the third interconnect, wherein the first bias is greater than the second bias.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 7, 2024
    Inventors: HSIANG-TAI LU, KUAN-LUNG WU, YU-WEI CHIU, WEN-CHIEN CHANG
  • Patent number: 12120886
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Sheng Tang, Wei-De Ho, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin
  • Publication number: 20240266266
    Abstract: A semiconductor structure includes: an interposer including an integrated passive device, a die-side redistribution structure, first on-interposer bump structures, and second on-interposer bump structures. First die-side redistribution wiring interconnects electrically connect electrical nodes within the integrated passive device to the first on-interposer bump structures. Second die-side redistribution wiring interconnects provide a respective electrical connection between a respective pair of second on-interposer bump structures. A first semiconductor die includes first on-die bump structures that are bonded to the first on-interposer bump structures through first solder material portions, and further includes second on-die bump structures that are bonded to the second on-interposer bump structures through second solder material portions.
    Type: Application
    Filed: May 24, 2023
    Publication date: August 8, 2024
    Inventors: Kuo-Ching Hsu, Hsiang-Tai Lu, Kuan-Lung Wu, Ya Huei Lee
  • Publication number: 20240238711
    Abstract: An electronic device includes a shell, a fan, a dust filter assembly, a wind speed sensor, and a controller. The shell includes an accommodation space. The fan is arranged in the accommodation space. The dust filter assembly is at least partially arranged at an air opening of the shell and is configured to filter dust. The wind speed sensor is arranged on a side of the air opening of the fan and is configured to detect a first flow rate of air on the side of the air opening of the fan. The controller is electrically connected to the wind speed sensor and is configured to determine whether the dust filter assembly needs to be cleaned based on the first flow rate and a determined flow rate.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 18, 2024
    Inventors: Chun Hsiang CHOU, Yi Lung WU, Hsiang Lung YU, Mone-Shune TSAI
  • Patent number: 11996297
    Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta Chen, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin
  • Publication number: 20240105518
    Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240085808
    Abstract: A particle removal method includes loading a particle attracting member with a coating layer into a processing chamber of a processing apparatus. The processing chamber is configured to perform a lithography exposure process on a semiconductor wafer. The method also includes fixing the particle attracting member on a reticle holder in the processing chamber in a cleaning cycle, attracting particles in the processing chamber by the coating layer of the particle attracting member due to a potential difference between the particles and the coating layer, and loading the particle attracting member with the coating layer and the attracted particles out of the processing chamber, after the cleaning cycle. The method also includes loading the semiconductor wafer into the processing chamber, and performing the lithography exposure process on the semiconductor wafer in the processing chamber using a reticle fixed on the reticle holder after the cleaning cycle.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Yuan YAO, Yu-Yu CHEN, Hsiang-Lung TSOU
  • Publication number: 20240030073
    Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Inventors: Wei-De HO, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
  • Patent number: 11852982
    Abstract: A semiconductor manufacturing system includes a semiconductor processing apparatus. The semiconductor processing apparatus includes a processing chamber configured to perform a semiconductor process on a semiconductor wafer, and a transferring module configured to transfer the semiconductor wafer into and out of the processing chamber. The semiconductor manufacturing system also includes a particle attracting member. The semiconductor manufacturing system also includes a monitoring device configured to control the transferring module to load the particle attracting member into the processing chamber in a cleaning cycle while the semiconductor wafer is not in the processing chamber, and control the transferring module to load the particle attracting member out of the processing chamber after the cleaning cycle.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yuan Yao, Yu-Yu Chen, Hsiang-Lung Tsou
  • Publication number: 20230402277
    Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Patent number: 11749570
    Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-De Ho, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
  • Publication number: 20230139799
    Abstract: In pattern formation method, a photomask is loaded into a lithography apparatus, an exposure light is applied to a photo resist layer formed over a substrate through or via the photomask, and the photo resist layer is developed. The photomask includes a plurality of octagonal shape patterns periodically arranged in a first direction and a second direction crossing the first direction. A width Lx of horizontal sides extending in the first direction of each of the plurality octagonal shape patterns is different from a width Ly of vertical sides extending in the second direction of each of the plurality octagonal shape patterns.
    Type: Application
    Filed: March 30, 2022
    Publication date: May 4, 2023
    Inventors: Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20230062426
    Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Wei-De HO, Pei-Sheng TANG, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN, Chen-Jung WANG
  • Publication number: 20230067049
    Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is fanned in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Sheng TANG, Wei-De HO, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20230049896
    Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.
    Type: Application
    Filed: April 5, 2022
    Publication date: February 16, 2023
    Inventors: Jin-Dah CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20220299890
    Abstract: A semiconductor manufacturing system includes a semiconductor processing apparatus. The semiconductor processing apparatus includes a processing chamber configured to perform a semiconductor process on a semiconductor wafer, and a transferring module configured to transfer the semiconductor wafer into and out of the processing chamber. The semiconductor manufacturing system also includes a particle attracting member. The semiconductor manufacturing system also includes a monitoring device configured to control the transferring module to load the particle attracting member into the processing chamber in a cleaning cycle while the semiconductor wafer is not in the processing chamber, and control the transferring module to load the particle attracting member out of the processing chamber after the cleaning cycle.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Inventors: Chih-Yuan YAO, Yu-Yu CHEN, Hsiang-Lung TSOU
  • Patent number: 11392745
    Abstract: A method of manufacturing an integrated circuit (IC) includes receiving a layout of the IC having a first region interposed between two second regions. The layout includes a first layer having first features and second and third layer having second and third features in the first region. The second and third features collectively form cut patterns for the first features. The method further includes modifying the second and third features by a mask house tool, resulting in modified second and third features, which collectively form modified cut patterns for the first features. The modifying of the second and third features meets at least one of following conditions: total spacing between adjacent modified second (third) features is greater than total spacing between adjacent second (third) features, and total length of the modified second (third) features is smaller than total length of the second (third) features.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Lin Wu, Cheng-Cheng Kuo, Chia-Ping Chiang, Chih-Wei Hsu, Hua-Tai Lin, Kuei-Shun Chen, Yuan-Hsiang Lung, Yan-Tso Tsai