Abstract: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.

Abstract: A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.

Abstract: A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix.

Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Abstract: A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element.

Abstract: A phase change memory device with improve thermal isolation. The device includes an electrode stack, including a first and second electrode elements, generally planar in form, separated by and in mutual contact with a dielectric spacer element, wherein the electrode stack includes a side surface; a phase change element having a bottom surface in contact with the electrode stack side surface, including electrical contact with the first and second electrode elements; and dielectric fill material surrounding and encasing the memory device, wherein the dielectric fill material is spaced from the phase change element, such that the phase change element and the dielectric fill material define a cavity adjacent the phase change element, and wherein the cavity contains a low pressure environment.

Abstract: A thermally insulated memory device comprises a memory cell, the memory cell having electrodes with a via extending therebetween, a thermal insulator within the via and defining a void extending between the electrode surfaces. A memory material, such as a phase change material, is within the void and electrically couples the electrodes to create a memory material element. The thermal insulator helps to reduce the power required to operate the memory material element. An electrode may contact the outer surface of a plug to accommodate any imperfections, such as the void-type imperfections, at the plug surface. Methods for making the device and accommodating plug surface imperfections are also disclosed.

Abstract: A memory device includes two electrodes, vertically separated and having mutually opposed contact surfaces, between which lies a phase change cell. The phase change cell includes an upper phase change member, having a contact surface in electrical contact with the first electrode; a lower phase change member, having a contact surface in electrical contact with the second electrode; and a kernel member disposed between and in electrical contact with the upper and lower phase change members. The phase change cell is formed of material having at least two solid phases, and the lateral extent of the upper and lower phase change members is substantially greater than that of the kernel member. An intermediate insulating layer is disposed between the upper and lower phase change members adjacent to the kernel member.

Abstract: A memory cell device includes a bottom electrode, pipe shaped member comprising phase change material and a top electrode in contact with the pipe-shaped member. An electrically and thermally insulating material is inside the pipe-shaped member. An integrated circuit including an array of pipe-shaped phase change memory cells is described.

Abstract: A manufacturing method for a pipe-shaped memory cell device includes forming a bottom electrode having a top surface; forming a fill layer over the electrode, with a via having sides, extending from a top surface of the fill layer to the top surface of the bottom electrode; forming a conformal layer of programmable resistive material within the via, the conformal layer contacting the electrode and extending along the sides of the via to the top surface; and forming a top electrode in contact with the conformal layer over the fill layer.

Abstract: A memory device comprising a first pan-shaped electrode having a side wall with a top side, a second pan-shaped electrode having a side wall with a top side and an insulating wall between the first side wall and the second side wall. The insulating wall has a thickness between the first and second side walls near the respective top sides. A bridge of memory material crosses the insulating wall, and defines an inter-electrode path between the first and second electrodes across the insulating wall. An array of such memory cells is provided. The bridges of memory material have sub-lithographic dimensions.

Abstract: A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.

Abstract: A memory device comprising a access circuits, an electrode layer over the access circuits, an array of phase change memory bridges over the electrode layer, and a plurality of bit lines over the array of phase change memory bridges. The electrode layer includes electrode pairs. Electrode pairs include a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member.

Abstract: A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. A bridge of memory material is formed on the top surface of the electrode layer across the insulating member for each memory cell to be formed. An access structure over the electrode layer is made by forming a patterned conductive layer over said bridge, and forming a contact between said first electrode and said patterned conductive layer.

Abstract: A charge trapping memory device in which a field induced inversion layer is used to replace the source and drain implants. The memory cell are adapted to store two bits, one on the left side and one on the right side of the charge trapping structure. A positive threshold voltage erase state is induced using negative gate voltage Fowler Nordheim FN tunneling which establishes a charge balance condition at a positive voltage. A low current, source side, hot electron injection programming method is used.

Abstract: The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalcogenide memory. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

Abstract: A method of forming a device comprises forming a structure with a side wall. A side wall spacer is formed on the side wall. The side wall spacer is etched according to a pattern to define the width of the side wall spacer. The width is sub-lithographic, including for example about 40 nanometers or less.

Abstract: Disclosed are use methods, integrated circuits, and manufacturing methods for ferroelectric memory. A data value from multiple data values is received, for example by a state machine controlling the ferroelectric memory. The different data values correspond to different particular durations. The data value corresponding to the selected particular duration is stored in a ferroelectric memory cell by applying voltage to the ferroelectric memory cell for the particular duration.

Abstract: A Trap Read Only Memory (TROM) architecture employs a NAND-type array structure configured as a read-only memory that is programmed only one time. The memory cells in the array comprise a gate terminal, a first channel terminal (source/drain), a second channel terminal (drain/source) and a channel region between the first and second channel terminals. A charge trapping structure, such as a layer of silicon nitride, is formed over the channel region. A tunneling dielectric is placed between the channel region and the charge trapping structure, and a blocking dielectric is placed between the charge trapping structure and the gate terminal. An E-field assisted (Fowler-Nordheim FN) tunneling program algorithm is applied.