Abstract: A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved.

Abstract: A nitride light-emitting diode (LED) fabrication method includes: providing a glass substrate; stacking a buffer layer structure composed of circular SiAlN layers and AlGaN layers with the number of cycles 1-5; growing a non-doped GaN layer, an N-type layer, a quantum well layer and a P-type layer. By using the low-cost glass the substrate that has a mature processing technology, and growing a SiAlN and an AlGaN buffer layer thereon, lattice mismatch constant between the substance and the epitaxial layer can be improved. Therefore, photoelectric property of the LED can be improved.

Abstract: A graphite wafer carrier for LED epitaxial wafer processes, having a plurality of wafer pocket profiles above the carrier for carrying the epitaxial wafer substrate. The inner edge of the wafer pocket profile is a concave step with a plurality of inward-extended support portions; and also has a graphite wafer carrier edge and an axle hole at the center of the graphite wafer carrier. The pocket profiles of different quantities and sizes can be arranged on the basis of different process parameters. The disclosed structure can reduce or eliminate airflow interference and improve the wafer edge yield.

Abstract: A nitride light-emitting diode (LED) structure includes a substrate, a buffer layer, an N-type layer, a stress release layer, a quantum well light-emitting layer and a P-type layer, wherein, between the N-type layer and the stress release layer, an electric field distribution layer is inserted, which is an n-doped multi-layer GaN structure with growth temperature equaling to or lower than that of the quantum well light-emitting layer; and GaN layers of different doping concentrations are applied to gradually reduce electric field concentration and make uniform spreading of current, thus enhancing electrostatic voltage endurance, reducing failure rate during usage, improving operational reliability and extending service life of the nitride semiconductor component.

Abstract: An LED epitaxial structure includes a substrate; a GaN nucleating layer; a superlattice buffer layer comprising a plurality pairs of alternately stacked AlGaN/n-GaN structures; an n-GaN layer; a MQW light-emitting layer, a p-GaN layer and a p-type contact layer. Al(n) represents Al composition value of the nth AlGaN/n-GaN superlattice buffer layer pair; N(n) represents n-type impurity concentration value of the nth AlGaN/n-GaN superlattice buffer layer pair; variation trend of Al(n) is from gradual increase to gradual decrease, and for N(n) is from gradual increase to gradual decrease.

Abstract: An LED epitaxial structure includes a substrate; a GaN nucleating layer; a superlattice buffer layer comprising a plurality pairs of alternately stacked AlGaN/n-GaN structures; an n-GaN layer; a MQW light-emitting layer, a p-GaN layer and a p-type contact layer. Al(n) represents Al composition value of the nth AlGaN/n-GaN superlattice buffer layer pair; N(n) represents n-type impurity concentration value of the nth AlGaN/n-GaN superlattice buffer layer pair; variation trend of Al(n) is from gradual increase to gradual decrease, and for N(n) is from gradual increase to gradual decrease.

Abstract: A graphite wafer carrier for LED epitaxial wafer processes, having a plurality of wafer pocket profiles above the carrier for carrying the epitaxial wafer substrate. The inner edge of the wafer pocket profile is a concave step with a plurality of inward-extended support portions; and also has a graphite wafer carrier edge and an axle hole at the center of the graphite wafer carrier. The pocket profiles of different quantities and sizes can be arranged on the basis of different process parameters. The disclosed structure can reduce or eliminate airflow interference and improve the wafer edge yield.