Patents by Inventor Hsiang-Po LIU

Hsiang-Po LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11631675
    Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: April 18, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Yu-Po Wang, Yi-Hao Chien, Hsiang-Po Liu
  • Publication number: 20220238526
    Abstract: A semiconductor memory structure includes a semiconductor substrate including an active region and a chop region. The semiconductor memory structure also includes an isolation structure disposed in the chop region, a first gate structure extending at least through the isolation structure in the chop region, and a second gate structure extending at least through the active region. The semiconductor memory structure also includes a doped region disposed in the active region. A first distance between the doped region and the first gate structure is shorter than a second distance between the doped region and the second gate structure.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 28, 2022
    Inventors: Yu-Po WANG, Yi-Hao CHIEN, Hsiang-Po LIU
  • Publication number: 20220005703
    Abstract: A semiconductor structure and its manufacturing method are provided. The method includes sequentially forming an insulating layer and a patterned mask layer on a substrate. The patterned cover curtain layer has an opening, and the opening includes a main body portion and two extension portions located at both ends of the main body portion. The method includes sequentially forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the insulating layer. The first sacrificial layer fills the extension portions and defines a recess in the main body portion. The second sacrificial layer is formed in the recess defined by the first sacrificial layer. The third sacrificial layer is formed on the first sacrificial layer located in the extension portions.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 6, 2022
    Inventors: Kai JEN, Hsiang-Po LIU