Abstract: A silicon carbide semiconductor device comprises a silicon carbide substrate, a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a plurality of trenches and a gate electrode. The first doped regions are disposed in the drift layer and form a plurality of first p-n junctions and a plurality of JFET regions with the drift layer. The second doped regions are disposed within the first doped regions and form a plurality of second p-n junctions with the first doped regions. The third doped regions are disposed in the first doped regions and adjacent to the second doped regions. The trenches penetrate into the drift layer and run horizontally through the JFET regions. The gate electrode is disposed over a main surface and in the trenches, which is electrically isolated from the drift layer by a gate insulating layer.

Abstract: A silicon carbide semiconductor device includes a drift layer, a first doped region, a second doped region, a gate trench, a third doped region and a gate electrode. The drift layer is disposed on a SiC substrate. The first doped region is disposed on the drift layer. The second doped region is disposed on the first doped region. The gate trench is extended from an upper surface of the second doped region through the first doped region and into the drift layer. The gate trench is formed in a manner dividing the drift layer into a plurality of mesas encircled by the gate trench, each of the mesas comprises a center portion and a plurality of leg portions extended from the center portion. The third doped region is arranged in the center portion of the mesa, and is disposed in the first doped region and adjacent to the second doped region. The gate electrode is arranged in the gate trench and dielectrically insulated from the first doped region, the second doped region and the drift layer by a gate insulator.

Abstract: A silicon carbide semiconductor device comprises a drift layer, a plurality of transistor cells and a gate structure. Each of the transistor cells comprises a first doped region, a second doped region, a third doped region and a fourth doped region. The first doped region is disposed in the drift layer. The second doped region is disposed in the first doped region. The third doped region is disposed in the first doped region and adjacent to the second doped region. The fourth doped region is disposed in or on the first doped region to form a channel region and is configured in a way such that the channel region is not fully depleted when a driving gate voltage applied to the semiconductor device is zero and the channel region is fully depleted when the driving gate voltage is less than a negative threshold voltage.

Abstract: A silicon carbide semiconductor device comprises a SiC substrate, a drift layer disposed on the substrate, a plurality of first doping regions formed near a surface of the drift layer, a plurality of second doping regions formed near the surface of the drift layer and between the first doping regions and a first metal layer disposed on the surface of the drift layer. The first metal layer forms an Ohmic contact with the second doped region. The drift layer has a first doping concentration of a first conductivity type and each of the second doping regions has a second doping concentration of the first conductivity type, which is higher than the first doping concentration. Each of the first doping regions has a first depth and each of the second doping regions has a second depth which is smaller than the first depth.

Abstract: A silicon carbide semiconductor device has an active area, a termination area surrounding the active area in a plan view. The silicon carbide semiconductor device comprises a SiC substrate, a drift layer, an insulating layer, a polysilicon layer, an interlayer dielectric layer disposed on the polysilicon layer, and a metal layer. The polysilicon layer includes a first portion disposed over the active area and a second portion disposed over the termination area. The metal layer includes a first portion disposed over the active area and a second portion disposed over the termination area. At least one of the second portion of the polysilicon layer and the second portion of the metal layer is configurated to electrically connect to at least one of a gate electrode and a source electrode.

Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or fed back from the power transistor device; wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

Abstract: A power transistor module includes a power transistor device and a control circuit. The control circuit is electrically connected to the power transistor device for providing at least one gate voltage to drive the power transistor device, and adjusting the at least one gate voltage in response to an output power of the power transistor module. When the output power is greater than a predetermined power load, the at least one gate voltage has a first swing amplitude; and when the output power is less than or equal to the predetermined power load the at least one gate voltage has a second swing amplitude less than the first swing amplitude.

Abstract: A power transistor module includes: a power transistor device and a control circuit electrically connected to the power transistor device. The control circuit provides at least one gate voltage to drive the power transistor device, and adjusts the gate voltage in response to at least one signal provided from an external device or feedbacked from the power transistor device: wherein the gate voltage is greater than a threshold voltage of the power transistor device, and a swing amplitude of the gate voltage is a monotonically increasing or decreasing function of the signal.

Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.

Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.

Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.

Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.

Abstract: A silicon carbide semiconductor device and method of manufacture thereof is made by providing a channel control zone which has impurity concentration distribution increased gradually from a first doping boundary to reach a maximum value between the first doping boundary and a second doping boundary, then decreased gradually toward the second doping boundary, so that the silicon carbide semiconductor device is formed with a lower conduction resistance and increased drain current without sacrificing threshold voltage.

Abstract: A silicon carbide field effect transistor includes a silicon carbide substrate, an n-type drift layer, a p-type epitaxy layer, a source region, a trench gate, at least one p-type doped region, a source, a dielectric layer and a drain. The p-type doped region is disposed at the n-type drift layer to be adjacent to one lateral side of the trench gate, and includes a first doped block and a plurality of second doped blocks arranged at an interval from the first doped block towards the silicon carbide substrate. Further, a thickness of the second doped blocks does not exceed 2 um. Accordingly, not only the issue of limitations posed by the energy of ion implantation is solved, but also an electric field at a bottom and a corner of the trench gate is effectively reduced, thereby enhancing the reliability of the silicon carbide field effect transistor.