Patents by Inventor Hsiang-Wei Lin

Hsiang-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12125457
    Abstract: A signal processing circuit, complying with DisplayPort standard and operated in a display device which is as a DisplayPort sink device, includes a main physical circuit, which is configured to receive a first signal from one of a plurality of DisplayPort connectors of the display device connected to a first DisplayPort source device and a plurality of auxiliary physical circuits. Only a first auxiliary physical circuit of the plurality of auxiliary physical circuits is enabled to receive a second signal from the DisplayPort connector connected to the first DisplayPort source device.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: October 22, 2024
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Wen-Chi Lin, Li-Wei Chen, Hsiang-Chih Chen, Pao-Yen Lin, Cheng-Wei Sung, Chung-Wen Hung
  • Patent number: 12094745
    Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yong-Jyu Lin, Fu-Hsien Li, Chen-Wei Lu, Chi-Feng Tung, Hsiang Yin Shen
  • Patent number: 12094744
    Abstract: Some implementations described herein provide a method that includes loading, from a load port and into a first buffer of a multiple-buffer overhead hoist transport (OHT) vehicle, a first transport carrier storing one or more processed wafers. The method includes unloading to the load port, while the first buffer retains the first transport carrier, and from a second buffer of the multiple-buffer OHT vehicle, a second transport carrier storing one or more wafers for processing. In other implementations, the method includes loading, into a first buffer of the multiple-buffer OHT vehicle, a first transport carrier storing one or more wafers for processing, while a semiconductor processing tool, associated with a load port, is processing one or more wafers associated with a second transport carrier. The method includes positioning the multiple-buffer OHT vehicle above the load port while the multiple-buffer OHT vehicle retains the first transport carrier in the first buffer.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan Wei Lin, Fu-Hsien Li, Chi-Feng Tung, Hsiang Yin Shen
  • Patent number: 12051646
    Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiang-Lun Kao, Hsiang-Wei Liu, Tai-I Yang, Jian-Hua Chen, Yu-Chieh Liao, Yung-Chih Wang, Tien-Lu Lin
  • Publication number: 20230326746
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 12, 2023
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11705327
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20230048536
    Abstract: A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.
    Type: Application
    Filed: January 3, 2022
    Publication date: February 16, 2023
    Inventor: Hsiang-Wei Lin
  • Publication number: 20230038952
    Abstract: A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.
    Type: Application
    Filed: January 5, 2022
    Publication date: February 9, 2023
    Inventor: Hsiang-Wei Lin
  • Publication number: 20220406656
    Abstract: A semiconductor structure includes a gate structure over a substrate. The structure also includes a source/drain epitaxial structure formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the gate structure. The structure also includes a metal layer formed over the contact structure. The structure also includes a cap layer formed over the metal layer. The structure also includes a first etch stop layer including a metal compound formed over the cap layer. The structure also includes a second etch stop layer including nitrogen formed over the first etch stop layer. The structure also includes a via structure that passes through the first etch stop layer and the second etch stop layer.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei LIN
  • Publication number: 20220230871
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11295948
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Publication number: 20210202235
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 11011414
    Abstract: A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a trench between the first conductive line and the second conductive line, and forming a first etch stop layer. The first etch stop layer extends into the trench. A second etch stop layer is formed over the first etch stop layer. The second etch stop layer extends into the trench, and the second etch stop layer is more conformal than the first etch stop layer. A dielectric material is filled into the trench and over the second etch stop layer. An air gap is formed in the dielectric material.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10964626
    Abstract: The present disclosure provides a method for forming a semiconductor structure. In accordance with some embodiments, the method includes providing a substrate and a conductive feature formed over the substrate; forming a low-k dielectric layer over the conductive feature; forming a contact trench aligned with the conductive feature; and selectively growing a sealing layer which is a monolayer formed on sidewalls of the contact trench.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ting Huang, Hsiang-Wei Lin
  • Patent number: 10950431
    Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Wan-Yi Kao, Chung-Chi Ko, Li Chun Te, Hsiang-Wei Lin, Te-En Cheng, Wei-Ken Lin, Guan-Yao Tu, Shu Ling Liao
  • Patent number: 10943868
    Abstract: A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsiang-Wei Lin
  • Patent number: 10879369
    Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin
  • Publication number: 20200350417
    Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventor: Hsiang-Wei Lin
  • Publication number: 20200251418
    Abstract: A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventor: Hsiang-Wei Lin
  • Patent number: 10720507
    Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiang-Wei Lin