Patents by Inventor Hsiang-Wei Tseng

Hsiang-Wei Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927248
    Abstract: A rotary apparatus includes a casing having a top sunk opening and an axial hole that are coaxially with each other along an axial line. A top adjusting disc unit is fixed in the top sunk opening, and has a top inner surrounding surface and a top outer surrounding surface. A top inner hole of the top inner surrounding surface extends along a central line parallel to and offset from the axial line. The top outer surrounding surface is non-coaxial with the top inner surrounding wall. A passive gear unit is disposed in the axial hole, and is driven by an active gear unit that is driven by a drive unit in the casing. The passive gear unit has an output shaft extending along the central line. A top bearing is clamped between the top support portion and the top inner surrounding surface of the top adjusting disc unit.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: March 12, 2024
    Assignee: TOYO AUTOMATION CO., LTD.
    Inventors: Lei Shih Shih, Hsiang-Wei Chen, Kun-Cheng Tseng
  • Patent number: 8680672
    Abstract: A semiconductor package is provided for carrying a sleeve member and a fan wheel axially coupled to the sleeve member so as to provide a heat dissipating function. The semiconductor package includes: a substrate; a coil module and at least an electronic component disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the coil module and the electronic component so as to prevent the coil module and the electronic component from disturbing air flow generated by the fan wheel during operation, thereby avoiding generation of noises or vibrations.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: March 25, 2014
    Assignee: Amtek Semiconductors Co., Ltd.
    Inventor: Hsiang-Wei Tseng
  • Publication number: 20140041909
    Abstract: A method for reducing roughens of the metals on a ceramic substrate having metal filled via holes, comprising forming via holes, a seed layer, and through film coating, exposure and development process followed by multiple steps of DC electroplating to achieve copper circuit with desired surface roughness.
    Type: Application
    Filed: July 17, 2013
    Publication date: February 13, 2014
    Inventors: Hsiang-Wei TSENG, Kuan-Chou Chen, Han-Chung Chang, Cheng-Feng Chou, Chan-Li Lin, Yuan-Chen Hsu
  • Patent number: 8488320
    Abstract: A semiconductor package includes: a substrate having a first surface and a second surface opposing the first surface, the first surface having a fan placement zone, a hole and a ventilation hole penetrating the substrate formed at the fan placement zone of the substrate; an electronic component disposed on the first surface surrounding the fan placement zone, the electronic component electrically connected to the substrate; an encapsulant formed on the electronic component and the first surface of the substrate, the encapsulant having an encapsulant opening exposing the fan placement zone; and a fan unit disposed in the encapsulant opening and electrically connected to the substrate. Since the electronic component is disposed on the substrate outside the fan placement zone, heat generated by the electronic component can efficiently dissipate while damage problems of over heat will not occur, and the overall height of the fan unit can thus be decreased.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: July 16, 2013
    Assignee: Amtek Semiconductors Co., Ltd.
    Inventor: Hsiang-Wei Tseng
  • Publication number: 20130049185
    Abstract: A semiconductor package is provided for carrying a sleeve member and a fan wheel axially coupled to the sleeve member so as to provide a heat dissipating function. The semiconductor package includes: a substrate; a coil module and at least an electronic component disposed on the substrate; and an encapsulant formed on the substrate for encapsulating the coil module and the electronic component so as to prevent the coil module and the electronic component from disturbing air flow generated by the fan wheel during operation, thereby avoiding generation of noises or vibrations.
    Type: Application
    Filed: March 23, 2012
    Publication date: February 28, 2013
    Applicant: AMTEK SEMICONDUCTORS CO., LTD.
    Inventor: Hsiang-Wei Tseng
  • Publication number: 20110292607
    Abstract: A semiconductor package includes: a substrate having a first surface and a second surface opposing the first surface, the first surface having a fan placement zone, a hole and a ventilation hole penetrating the substrate formed at the fan placement zone of the substrate; an electronic component disposed on the first surface surrounding the fan placement zone, the electronic component electrically connected to the substrate; an encapsulant formed on the electronic component and the first surface of the substrate, the encapsulant having an encapsulant opening exposing the fan placement zone; and a fan unit disposed in the encapsulant opening and electrically connected to the substrate. Since the electronic component is disposed on the substrate outside the fan placement zone, heat generated by the electronic component can efficiently dissipate while damage problems of over heat will not occur, and the overall height of the fan unit can thus be decreased.
    Type: Application
    Filed: May 18, 2011
    Publication date: December 1, 2011
    Applicant: AMTEK SEMICONDUCTORS CO., LTD.
    Inventor: Hsiang-Wei Tseng
  • Patent number: 6391737
    Abstract: A method of manufacturing semiconductor devices. An alignment mark is formed in any one of the dies in a substrate. A waiting-for-patterning layer is formed over the dies. A negative photoresist layer is formed over the waiting-for-patterning layer. A first exposure is carried out so that a plurality of first exposed regions is formed in all the dies of the chip. A second exposure is carried out to form a second exposed region. The second exposed region overlaps with the first exposed region and the unexposed region above the alignment mark and the overlapping region covers the alignment mark region. A photoresist development is conducted to remove the negative photoresist in the unexposed regions. Using the negative photoresist as a mask, a portion of the waiting-for-patterning layer is removed to form a pattern on the waiting-for-patterning layer. The negative photoresist layer is removed.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: May 21, 2002
    Assignee: Vanguard International Semiconductor Corp.
    Inventors: Chin-Yu Ku, Hsiang-Wei Tseng
  • Patent number: 5985363
    Abstract: A method for providing a uniform coating of photoresist over substrate for defining high density integrated device and circuit patterns. This is accomplished by applying the photoresist onto the substrate in multiple, separate dispensing steps and leveling spins to attain the designed thickness uniformly over substrate having high topographic surfaces, thereby preserve the integrity of the critical dimension for multi-level alignments used in the fabrication of integrated devices and circuits.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: November 16, 1999
    Assignee: Vanguard International Semiconductor
    Inventors: Gwo-Yuh Shiau, Shinn-Jhy Lian, Daniel Hao-Tien Lee, Li-Ming Wang, Hsiang-Wei Tseng
  • Patent number: 5851877
    Abstract: An etching process is used to etch the polysilicon layer. Then, Polymers are formed on the polysilicon layer after an ash step is performed. An organic layer is formed on the surface of the polysilicon layer, and on the polymers. An anisotropically etch is carried out to etch the organic layer, thereby forming organic side wall spacers on the side walls of the polysilicon layer. The etching is continuously performed to etch the polysilicon layer using the polymers and organic side wall spacers as masks. Next, an ash and a RCA clean procedure are performed to remove the residual polymers and the organic layer. A dielectric layer is then deposited on the surface of the polysilicon. A conductive layer is deposited over the dielectric layer.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: December 22, 1998
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Chun Ho, Hsiang-Wei Tseng