Abstract: Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.

Abstract: Systems, methods, and other embodiments associated with mitigating wire capacitance are described. In one embodiment, a method includes loading, by at least a processor into an electronic memory, an electronic data structure that includes a design of an integrated circuit. The design defines layers of the integrated circuit and connections between structures and wire interconnects in the layers. The example method may also include generating, by at least the processor, a structured topology in the design by successively routing the wire interconnects throughout the layers according to coordinates of the structures in the design and weighted values associated with each of the structures to mitigate wire capacitance of the wire interconnects.