Patents by Inventor Hsiang-Yi Hsieh

Hsiang-Yi Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8327313
    Abstract: A re-routing method for a circuit diagram includes the following steps. At least one pair of the signal lines is obtained from a routed circuit diagram. The routed circuit diagram is adapted to be laid out on a substrate of a Printed Circuit Board (PCB). The substrate includes warp wires and weft wires. At least one pair of the signal lines includes two signal lines in parallel. The pair of signal lines includes several pairs of line segments. It is determined whether at least one pair of parallel line segments exists in the pairs of line segments parallel to the warp or weft wires. If at least one pair of parallel line segments exists, at least one pair of parallel line segments on the routed circuit diagram is replaced with several pairs of 10-degree lines. Respective angle between the 10-degree lines and the warp or weft wires are 10 degrees.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: December 4, 2012
    Assignee: Inventec Corporation
    Inventor: Hsiang-Yi Hsieh
  • Publication number: 20120096422
    Abstract: A re-routing method for a circuit diagram includes the following steps. At least one pair of the signal lines is obtained from a routed circuit diagram. The routed circuit diagram is adapted to be laid out on a substrate of a Printed Circuit Board (PCB). The substrate includes warp wires and weft wires. At least one pair of the signal lines includes two signal lines in parallel. The pair of signal lines includes several pairs of line segments. It is determined whether at least one pair of parallel line segments exists in the pairs of line segments parallel to the warp or weft wires. If at least one pair of parallel line segments exists, at least one pair of parallel line segments on the routed circuit diagram is replaced with several pairs of 10-degree lines. Respective angle between the 10-degree lines and the warp or weft wires are 10 degrees.
    Type: Application
    Filed: January 7, 2011
    Publication date: April 19, 2012
    Applicant: INVENTEC CORPORATION
    Inventor: Hsiang-Yi HSIEH
  • Patent number: 7562317
    Abstract: A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided Design) circuit layout design program, for providing a CAD-created circuit layout diagram with a multitasking silkscreen text handling capability, which is characterized in that the task of the definition and modification of the silkscreen text associated with the circuit layout diagram can be conducted by multiple users separately from the task of the modification of the contents of the circuit layout diagram. By the prior art, these two tasks are inherently related to each other. This feature allows the circuit layout design with CAD to be less laborious and time-consuming and thus more efficient.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: July 14, 2009
    Assignee: Inventec Corporation
    Inventor: Hsiang-Yi Hsieh
  • Patent number: 7496873
    Abstract: A method and system is proposed for determining the required quantity of testing points on a circuit layout diagram generated by a computer-aided circuit layout design program on a computer platform. The proposed method and system is characterized by the use of a graphic file scanning method for finding and totaling the number of all the electrical connecting points associated with each electronic component in the circuit layout diagram, whereby the required quantity of testing points is determined based on the total of the electrical connecting points. The determined quantity of testing points is then informed to the user by displaying it in a human-readable form on the computer platform. This feature allows circuit layout design to be less laborious and time-consuming and thus more efficient than prior art.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: February 24, 2009
    Assignee: Inventec Corporation
    Inventor: Hsiang-Yi Hsieh
  • Publication number: 20080109778
    Abstract: A setting method of line pitch/line width layout for a logic circuit is provided. In the setting method, a circuit integration procedure is utilized to find the conformable circuit code and retrieve the corresponding circuit setting by string comparison from a logic circuit setting file, so as to integrally generate a first layout setting file. Then an area restriction rule is loaded for adjusting the first layout setting file in order to form a second layout file. The second layout file is transmitted to the logic circuit software. Thus, the user may rapidly obtain the circuit layout setting and uses it in the logic circuit software. Therefore, not only lots of pre-operation time can be reduced, but the situations of wrong inputting of setting value are also reduced.
    Type: Application
    Filed: October 23, 2006
    Publication date: May 8, 2008
    Applicant: INVENTEC CORPORATION
    Inventor: Hsiang-Yi Hsieh
  • Publication number: 20080092102
    Abstract: A multitasking circuit layout diagram silkscreen text handling method and system is proposed, which is designed for use in conjunction with a computer platform that runs a CAD (Computer-Aided Design) circuit layout design program, for providing a CAD-created circuit layout diagram with a multitasking silkscreen text handling capability, which is characterized in that the task of the definition and modification of the silkscreen text associated with the circuit layout diagram can be conducted by multiple users separately from the task of the modification of the contents of the circuit layout diagram. By the prior art, these two tasks are inherently related to each other. This feature allows the circuit layout design with CAD to be less laborious and time-consuming and thus more efficient.
    Type: Application
    Filed: October 12, 2006
    Publication date: April 17, 2008
    Applicant: INVENTEC CORPORATION
    Inventor: Hsiang-Yi Hsieh
  • Publication number: 20080028346
    Abstract: A method and system is proposed for determining the required quantity of testing points on a circuit layout diagram generated by a computer-aided circuit layout design program on a computer platform. The proposed method and system is characterized by the use of a graphic file scanning method for finding and totaling the number of all the electrical connecting points associated with each electronic component in the circuit layout diagram, whereby the required quantity of testing points is determined based on the total of the electrical connecting points. The determined quantity of testing points is then informed to the user by displaying it in a human-readable form on the computer platform. This feature allows circuit layout design to be less laborious and time-consuming and thus more efficient than prior art.
    Type: Application
    Filed: November 8, 2006
    Publication date: January 31, 2008
    Applicant: INVENTEC CORPORATION
    Inventor: Hsiang-Yi Hsieh