Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A high/low beam switching device generally includes a fixing plate, a solenoid device, a shielding member, and a coil spring. The fixing plate defines an opening which is divided into three zones including an upper space, a middle space, and a lower space. The solenoid device is horizontally disposed in a frame fixed on a shelf extending from the fixing plate. The shielding member, which can cover the middle space of the fixing plate, is pivotally connected to the fixing plate. The solenoid device when being energized can turn the shielding member to uncover the middle space, so that a high beam illumination pattern can be provided. When the solenoid device is de-energized, the shielding member can be turned back to the fixing plate to cover the middle space, so that a low beam illumination pattern can be provided. Also, the present invention provides a headlamp including the switching device.

Abstract: A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.

Abstract: A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.

Abstract: A network switching apparatus and method for congestion control. Each one of the connection ports of the switching apparatus includes a low priority queue and a high priority queue. When a data packet enters a switching apparatus, the switching apparatus according to the type of the data packet enqueues the data packet to the low priority queue or the high priority queue. When congestion occurs at the switching apparatus, the low priority queue and the high priority queue can respectively perform the different ways of the congestion control, according to the input congestion mode. Also, when the switching apparatus receives a pause frame, response flow control can be performed, according to the output congestion mode. Since the different ways of the congestion control are performed according to the different types of the data packet, the congestion control can be optimized.

Abstract: An Ethernet switch with rate control and associated method is provided. Each port in the switch has individual settings of egress/ingress) rate control, which are stored in a register and configured based on required rates. The switch uses data volume that a port can output/input within each unit time to control egress/ingress rate of the port. Further, the egress rate can be precisely controlled by using uniform random numbers provided by an random number generator of the switch, and the ingress rate can be advantageously controlled by combining a proper kind of congestion control, which is performed according to the capability of a device connected to the port, such as full-duplex or half-duplex, and flow control.

Abstract: A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS path receives and passes a data strobe signal. The delay element is coupled to the DQS path, receiving the data strobe signal to generate a compensated data strobe signal having a calibrated latency. The calibrated latency is determined by an adjustment signal. The flip flop is coupled to the data signal path and the delay element, sampling the delayed data signal by the compensated data strobe signal to generate an output data. The adjustment unit generates the adjustment signal according to the output data. The adjustment unit performs a calibration to adjust the adjustment signal, thus the calibrated latency is adjusted.

Abstract: A method and related apparatus for reordering access requests used to access main memory of a data processing system. The method includes receiving one or more access requests for accessing the memory device in a first predetermined order, and reordering the access requests in a second predetermined order to be processed in a request queue by relocating a first access request to follow a second access request accessing a same memory page to increase processing efficiency. In addition, the relocating is prohibited if it increases a processing latency for a third access request to exceed a predetermined limit.

Abstract: A method for a graphics chip to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs N?1 page switching operations.

Abstract: A method for a display controller to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs N−1 page switching operations.

Abstract: A method and related apparatus for reordering access requests used to access main memory of a data processing system. The method includes receiving one or more access requests for accessing the memory device in a first predetermined order, and reordering the access requests in a second predetermined order to be processed in a request queue by relocating a first access request to follow a second access request accessing a same memory page to increase processing efficiency. In addition, the relocating is prohibited if it increases a processing latency for a third access request to exceed a predetermined limit.

Abstract: The present invention discloses a switching apparatus and method using bandwidth decomposition, appling a von Neumann algorithm, a Birkhoff theorem, a Packetized Generalized Processor Sharing algorithm, a water filling algorithm and a dynamnically calculating rate algorithm in packet switching of a high speed network. It is not necessary to speed up internally and determine a maximal matching between input ports and output ports for the switching apparatus and method using bandwidth decomposition according to the present invention, so the executing speed of a network using the present appatatus and method will be increased, and the manufacturing of the present invention can be easily implemented by current VLSI technology.

Abstract: An Ethernet switch with rate control and associated method is provided. Each port in the switch has individual settings of egress/ingress) rate control, which are stored in a register and configured based on required rates. The switch uses data volume that a port can output/input within each unit time to control egress/ingress rate of the port. Further, the egress rate can be precisely controlled by using uniform random numbers provided by an random number generator of the switch, and the ingress rate can be advantageously controlled by combining a proper kind of congestion control, which is performed according to the capability of a device connected to the port, such as full-duplex or half-duplex, and flow control.

Abstract: A network switching apparatus and method for congestion control. Each one of the connection ports of the switching apparatus includes a low priority queue and a high priority queue. When a data packet enters a switching apparatus, the switching apparatus according to the type of the data packet enqueues the data packet to the low priority queue or the high priority queue. When congestion occurs at the switching apparatus, the low priority queue and the high priority queue can respectively perform the different ways of the congestion control, according to the input congestion mode. Also, when the switching apparatus receives a pause frame, response flow control can be performed, according to the output congestion mode. Since the different ways of the congestion control are performed according to the different types of the data packet, the congestion control can be optimized.