Patents by Inventor Hsiang-Ying Wang
Hsiang-Ying Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8431460Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.Type: GrantFiled: May 27, 2011Date of Patent: April 30, 2013Assignee: United Microelectronics Corp.Inventors: Shin-Chuan Huang, Guang-Yaw Hwang, Hsiang-Ying Wang, Yu-Hsiang Hung, I-Chang Wang
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Publication number: 20120299058Abstract: A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.Type: ApplicationFiled: May 27, 2011Publication date: November 29, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chuan Huang, Guang-Yaw Hwang, Hsiang-Ying Wang, Yu-Hsiang Hung, I-Chang Wang
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Patent number: 8076210Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.Type: GrantFiled: March 8, 2011Date of Patent: December 13, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 8053847Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.Type: GrantFiled: November 28, 2008Date of Patent: November 8, 2011Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Publication number: 20110159658Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a first ion implantation process to implant a first molecular cluster having carbon, boron, and hydrogen into the semiconductor substrate at two sides of the gate structure for forming a doped region, wherein the molecular weight of the first molecular cluster is greater than 100.Type: ApplicationFiled: March 8, 2011Publication date: June 30, 2011Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 7795101Abstract: A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO2.Type: GrantFiled: February 8, 2010Date of Patent: September 14, 2010Assignee: United Microelectronics Corp.Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Publication number: 20100144110Abstract: A method of forming a MOS transistor, in which, a co-implantation is performed to implant a carbon co-implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect, and the carbon co-implant is from a precursor comprising CO or CO2.Type: ApplicationFiled: February 8, 2010Publication date: June 10, 2010Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Publication number: 20090101894Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing carbon, boron, and hydrogen into the semiconductor substrate at two sides of the spacer for forming a doped region. The molecular weight of the molecular cluster is preferably greater than 100. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the doped region.Type: ApplicationFiled: November 28, 2008Publication date: April 23, 2009Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 7473606Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.Type: GrantFiled: February 15, 2007Date of Patent: January 6, 2009Assignee: United Microelectronics Corp.Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Publication number: 20080258178Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of CO, CO2, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of to 1000.Type: ApplicationFiled: May 27, 2008Publication date: October 23, 2008Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Patent number: 7435658Abstract: A method of manufacturing a MOS transistor is provided. A substrate having a gate structure thereon is provided. A first spacer is formed on the sidewall of the gate structure. A pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer. A doped source/drain region is formed in the substrate on each side of the second spacer. Thereafter, a solid phase epitaxial process is carried out to re-crystallize the amorphized portion of the substrate and activate the doped source/drain extension region and the doped source/drain region to form a source/drain terminal. Finally, a post-annealing operation is performed.Type: GrantFiled: June 7, 2005Date of Patent: October 14, 2008Assignee: United Microelectronics Corp.Inventors: Yu-Ren Wang, Chin-Cheng Chien, Hsiang-Ying Wang, Neng-Hui Yang
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Patent number: 7396717Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, Chd xHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.Type: GrantFiled: April 3, 2006Date of Patent: July 8, 2008Assignee: United Microelectronics Corp.Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Publication number: 20070238234Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.Type: ApplicationFiled: April 3, 2006Publication date: October 11, 2007Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Publication number: 20070228464Abstract: A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.Type: ApplicationFiled: May 14, 2007Publication date: October 4, 2007Inventors: Hsiang-Ying Wang, Chin-Cheng Chien, Tsai-Fu Hsiao, Ming-Yen Chien, Chao-Chun Chen
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Publication number: 20070196990Abstract: A method for fabricating a metal-oxide semiconductor transistor is disclosed. First, a semiconductor substrate having a gate structure thereon is provided, and a spacer is formed around the gate structure. An ion implantation process is performed to implant a molecular cluster containing boron into the semiconductor substrate surrounding the spacer for forming a source/drain region. The weight ratio of each boron atom within the molecular cluster is preferably less than 10%. Thereafter, a millisecond annealing process is performed to activate the molecular cluster within the source/drain region.Type: ApplicationFiled: February 15, 2007Publication date: August 23, 2007Inventors: Tsai-Fu Hsiao, Ching-I Li, Po-Yuan Chen, Chun-An Lin, Hsiang-Ying Wang, Chao-Chun Chen, Chin-Cheng Chien
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Patent number: 7176504Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer is deposited on the sidewalls of the gate structure. The SixGey layer is deposited in the substrate on both sides of the spacer and extended to a portion beneath part of the spacer. In addition, the top level of the SixGey layer is higher than the surface of the substrate. Moreover, the SixGey protection layer is deposited on the SixGey layer and the SixGey protection layer comprises Six1Gey1, where 0?y1<y.Type: GrantFiled: September 28, 2005Date of Patent: February 13, 2007Assignee: United Microelectronics Corp.Inventors: Huan-Shun Lin, Hung-Lin Shih, Hsiang-Ying Wang, Jih-Shun Chiang, Min-Chi Fan
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Publication number: 20060189167Abstract: A method for fabricating a silicon nitride film is disclosed. The method is adapted for a substrate comprising a transistor device. A self-aligned silicide film is formed over the transistor device. A silicon nitride film is then formed over the substrate. A thermal process is performed to the silicon nitride film. The process temperature of the thermal treatment process is lower than 450° C. and the thermal treatment process is performed under an inert gas environment. According to the fabrication method of the present invention, a high tensile stress silicon nitride film can be formed by a process with a low thermal budget. The electron mobility in the channel region of the transistor device can be enhanced without affecting the thermal stability of metal silicide.Type: ApplicationFiled: February 18, 2005Publication date: August 24, 2006Inventors: Hsiang-Ying Wang, Neng-Hui Yang, Huan-Shun Lin
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Patent number: 7071046Abstract: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.Type: GrantFiled: November 18, 2004Date of Patent: July 4, 2006Assignee: United Microelectronics Corp.Inventors: Neng-Hui Yang, Huan-Shun Lin, Hsiang-Ying Wang
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Patent number: 7060547Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.Type: GrantFiled: January 27, 2004Date of Patent: June 13, 2006Assignee: United Microelectronics Corp.Inventors: Yu-Kun Chen, Neng-Hui Yang, Chin-Cheng Chien, Hsiang-Ying Wang
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Publication number: 20060105511Abstract: A method of manufacturing a MOS transistor, comprising the steps of providing a semiconductor substrate, forming a gate structure on the semiconductor substrate, performing an implantation to form two implanted regions in the semiconductor substrate respectively adjacent to the gate structure, performing an etching process to remove each implanted region and form a trench, and performing a selective epitaxial growth to fill epitaxial crystal into the trenches, thereby forming a source/drain of the MOS transistor.Type: ApplicationFiled: November 18, 2004Publication date: May 18, 2006Inventors: Neng-Hui Yang, Huan-Shun Lin, Hsiang-Ying Wang