Patents by Inventor Hsiang-Yu Lai

Hsiang-Yu Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20240063294
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a plurality of dummy gates over a substrate and performing a first etch step and a second etch step on the substrate exposed between the dummy gates. The first etch step includes an anisotropic etching process and an isotropic etching process. The second includes an isotropic etching step.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Ta-Chun LIN, Jyun-Yang SHEN, Hsiang-Yu LAI, Shih-Chang TSAI, Chun-Jun LIN, Kuo-Hua PAN, Jhon Jhy LIAW
  • Memory device and method for fabricating the same
    Patent number: 9530784
    Abstract: Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers. The first conductive layers and the dielectric layers are stacked alternately. The first cap layers are located on sidewalls of the first conductive layers respectively. The second cap layers are located on sidewalls of the dielectric layers respectively.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: December 27, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hsiang-Yu Lai, Zu-Sing Yang
  • MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    Publication number: 20160372480
    Abstract: Provided is a memory device including a stack structure, a plurality of first cap layers, and a plurality of second cap layers. The stack structure is located on a substrate. The stack structure includes a plurality of first conductive layers and a plurality of dielectric layers. The first conductive layers and the dielectric layers are stacked alternately. The first cap layers are located on sidewalls of the first conductive layers respectively. The second cap layers are located on sidewalls of the dielectric layers respectively.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventors: Hsiang-Yu Lai, Zu-Sing Yang