Patents by Inventor Hsiang-Yun Huang

Hsiang-Yun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Patent number: 9167232
    Abstract: A 2D video to 3D video conversion system includes a video content analysis unit, a depth estimation unit, a post-processing unit, and a stereoscopic video generation unit. The video content analysis unit can analyze a 2D video datum and extract useful information including motion and color from the 2D video datum for depth estimation. The depth estimation unit is adapted for receiving the useful information, calculating motion cue and contrast cue for initial depth estimation, and generating an initial depth map. The post-processing unit is adapted for correcting the initial depth map in spatial domain and temporal domain to increase accuracy in spatial domain and depth continuity between adjacent time instances and for processing the caption in the video to generate a final depth map. The stereoscopic video generation unit is adapted for synthesizing 3D video datum from the final depth map and 2D video datum.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: October 20, 2015
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Wen-Nung Lie, Hsiang-Yun Huang, Wei-Chih Chen
  • Publication number: 20130162768
    Abstract: A 2D video to 3D video conversion system includes a video content analysis unit, a depth estimation unit, a post-processing unit, and a stereoscopic video generation unit. The video content analysis unit can analyze a 2D video datum and extract useful information including motion and color from the 2D video datum for depth estimation. The depth estimation unit is adapted for receiving the useful information, calculating motion cue and contrast cue for initial depth estimation, and generating an initial depth map. The post-processing unit is adapted for correcting the initial depth map in spatial domain and temporal domain to increase accuracy in spatial domain and depth continuity between adjacent time instances and for processing the caption in the video to generate a final depth map. The stereoscopic video generation unit is adapted for synthesizing 3D video datum from the final depth map and 2D video datum.
    Type: Application
    Filed: July 6, 2012
    Publication date: June 27, 2013
    Inventors: Wen-Nung LIE, Hsiang-Yun Huang, Wei-Chih Chen
  • Patent number: 8042069
    Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: October 18, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen
  • Publication number: 20100036644
    Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.
    Type: Application
    Filed: August 7, 2008
    Publication date: February 11, 2010
    Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen