Patents by Inventor Hsiang-Chih Hsiao
Hsiang-Chih Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190087644Abstract: The present invention is directed to an adaptive method for object detection. A predetermined number of next window images following a current window image are skipped, if a current likelihood value is less than a predetermined background threshold. The object detection early terminates, if a previous window image preceding the current window image contains the object to be detected and the current likelihood value is greater than or equal to a predetermined foreground threshold.Type: ApplicationFiled: September 15, 2017Publication date: March 21, 2019Inventors: Ming-Der Shieh, Chun-Wei Chen, Hsiang-Chih Hsiao, Der-Wei Yang
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Patent number: 10230001Abstract: Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain which are spaced apart from each other; a semi-conductor layer arranged between the source and the drain; a first gate layer located on a side of the semi-conductor layer; and a second gate layer located on the other side of the semi-conductor layer. The field effect transistor provided by the present disclosure is less energy-consuming; a method for manufacturing the same is low costing; and a display device using the same is also less energy-consuming.Type: GrantFiled: May 19, 2015Date of Patent: March 12, 2019Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Hongyuan Xu, Hsiang Chih Hsiao, Chang I Su
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Publication number: 20170104104Abstract: Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain which are spaced apart from each other; a semi-conductor layer arranged between the source and the drain; a first gate layer located on a side of the semi-conductor layer; and a second gate layer located on the other side of the semi-conductor layer. The field effect transistor provided by the present disclosure is less energy-consuming; a method for manufacturing the same is low costing; and a display device using the same is also less energy-consuming.Type: ApplicationFiled: May 19, 2015Publication date: April 13, 2017Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventors: Hongyuan Xu, Hsiang Chih Hsiao, Chang I Su
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Patent number: 9437435Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.Type: GrantFiled: November 14, 2014Date of Patent: September 6, 2016Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xiaoxiao Wang, Hsiang Chih Hsiao, Peng Du, Chang-I Su, Hongyuan Xu, Bo Sun
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Patent number: 9341950Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: GrantFiled: May 27, 2015Date of Patent: May 17, 2016Assignee: Au Optronics CorporationInventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Publication number: 20160133473Abstract: The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.Type: ApplicationFiled: November 14, 2014Publication date: May 12, 2016Inventors: Xiaoxiao WANG, Hsiang Chih HSIAO, Peng DU, Chang-I SU, Hongyuan XU, Bo SUN
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Publication number: 20150253672Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: ApplicationFiled: May 27, 2015Publication date: September 10, 2015Inventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Patent number: 9122162Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: GrantFiled: March 15, 2013Date of Patent: September 1, 2015Assignee: Au Optronics CorporationInventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Patent number: 8669558Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.Type: GrantFiled: January 12, 2012Date of Patent: March 11, 2014Assignee: AU Optronics Corp.Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang
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Publication number: 20130235316Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: ApplicationFiled: March 15, 2013Publication date: September 12, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Tzu-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Patent number: 8530144Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.Type: GrantFiled: March 8, 2012Date of Patent: September 10, 2013Assignee: AU Optronics Corp.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Patent number: 8427631Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: GrantFiled: November 17, 2010Date of Patent: April 23, 2013Assignee: Au Optronics CorporationInventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Chi-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Patent number: 8377766Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.Type: GrantFiled: March 3, 2010Date of Patent: February 19, 2013Assignee: AU Optronics Corp.Inventors: Chia-Ming Chang, Hsiang-Chih Hsiao
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Publication number: 20120292622Abstract: A pixel structure includes a thin film transistor device, an insulating layer disposed on the thin film transistor device, and a pixel electrode disposed on the insulating layer. The thin film transistor device includes a floating conductive pad disposed at one side of a semiconductor layer, and electrically connected to a source/drain electrode. The insulating layer has a first contact hole partially exposing the floating conductive pad. The pixel electrode is electrically connected to the floating conductive pad via the first contact hole.Type: ApplicationFiled: January 12, 2012Publication date: November 22, 2012Inventors: Ching-Yang Liu, Wei-Hsiang Lin, Shu-Wei Chu, Hsiang-Chih Hsiao, Jhih-Jie Huang, Sai-Chang Liu, Yu-Hsing Liang
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Publication number: 20120270397Abstract: A method is provided for fabricating source/drain electrodes of a thin film transistor. The method generally provides a substrate having a first gate electrode and a second gate electrode adjacent and electrically connected. The method further provides coating a photoresist layer on the metal layer, and performing an exposure process on the photoresist layer by a photomask. The method further performs a development process on the exposed photoresist layer to form a photoresist pattern layer with different thicknesses on the metal layer, and then etches the metal layer using the photoresist pattern layer as an etch mask, to form a pair of first source/drain electrodes on the first gate electrode and a pair of second source/drain electrodes on the second gate electrode.Type: ApplicationFiled: March 8, 2012Publication date: October 25, 2012Applicant: AU OPTRONICS CORP.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Patent number: 8153337Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.Type: GrantFiled: December 3, 2009Date of Patent: April 10, 2012Assignee: AU Optronics Corp.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Publication number: 20110223393Abstract: An exposure apparatus is provided and adapted for exposing a photoresist layer on a layer to form a plurality of strip exposed patterns. The exposure apparatus includes a light source, a lens group and a mask. The lens group is disposed between the photoresist layer and the light source and includes a plurality of strip lens parallel to each other, wherein an overlapping region between any two neighboring strip lens is defined as a lens connecting region, and the other regions excluding the lens connecting regions are defined as lens regions. The mask is disposed between the photoresist layer and the lens group and includes a plurality of shielding patterns, wherein an outline of the shielding patterns corresponds to the strip exposed patterns, each shielding pattern has a strip opening, and an extension direction of the strip openings is substantially parallel to an extension direction of the shielding patterns.Type: ApplicationFiled: November 17, 2010Publication date: September 15, 2011Applicant: Au Optronics CorporationInventors: Hsiang-Chih Hsiao, Ta-Wen Liao, Chi-Min Yang, Shan-Fang Chen, Ya-Ping Chang, Chi-Hung Yang, Chung-Yuan Liao
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Patent number: 7989243Abstract: A pixel structure fabricating method is provided. A gate is formed on a substrate. A gate insulation layer covering the gate is formed on the substrate. A channel layer, a source, and a drain are simultaneously formed on the gate insulation layer above the gate. The gate, channel layer, source, and drain form a thin film transistor (TFT). A passivation layer is formed on the TFT and the gate insulation layer. A black matrix is formed on the passivation layer. The black matrix has a contact opening above the drain and a color filter containing opening. A color filer layer is formed within the color filter containing opening through inkjet printing. A dielectric layer is formed on the black matrix and the color filter layer. The dielectric layer and the passivation layer are patterned to expose the drain. A pixel electrode electrically connected to the drain is formed.Type: GrantFiled: March 5, 2009Date of Patent: August 2, 2011Assignee: Au Optronics CorporationInventors: Ta-Wen Liao, Chen-Pang Tung, Chia-Ming Chang, Zong-Long Jhang, Che-Yung Lai, Chun-Yi Chiang, Chou-Huan Yu, Hsiang-Chih Hsiao, Han-Tang Chou, Jun-Kai Chang
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Publication number: 20110053323Abstract: A photomask for fabricating a thin film transistor (TFT) is disclosed. The photomask includes a translucent layer disposed on a transparent substrate and covering U-shaped and rectangular channel-forming regions of the transparent substrate. First and second light-shielding layers are disposed on the translucent layer and located at the outer and inner sides of the U-shaped channel-forming region, respectively, and third and fourth light-shielding layers are disposed on the translucent layer and located at opposite sides of the rectangular channel-forming region, respectively, to serve as source/drain-forming regions. An end of the third light-shielding layer extends to the first light-shielding layer. A plurality of first light-shielding islands is disposed on the translucent layer and located within the rectangular channel-forming region. A method for fabricating source/drain electrodes of a TFT is also disclosed.Type: ApplicationFiled: December 3, 2009Publication date: March 3, 2011Applicant: AU OPTRONICS CORP.Inventors: Zong-Long Jhang, Chia-Ming Chang, Hsiang-Chih Hsiao, Chun-Yi Chiang, Che-Yung Lai, Chou-Huan Yu, Ta-Wen Liao
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Publication number: 20100320464Abstract: A photo-mask includes a first opaque pattern, a second opaque pattern, a transparent single slit, and a translucent pattern. The transparent single slit is disposed between the first opaque pattern and the second opaque pattern, and the width of the transparent single slit is substantially between 1.5 micrometers and 2.5 micrometers. The translucent pattern is connected to the first opaque pattern and the second opaque pattern.Type: ApplicationFiled: March 3, 2010Publication date: December 23, 2010Inventors: Chia-Ming Chang, Hsiang-Chih Hsiao