Patents by Inventor Hsiao-An Chuang
Hsiao-An Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240186320Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.Type: ApplicationFiled: February 14, 2024Publication date: June 6, 2024Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
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Publication number: 20240128313Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
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Patent number: 11948949Abstract: In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.Type: GrantFiled: July 15, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Hsiao-Hui Tseng, Jen-Cheng Liu, Jhy-Jyi Sze, Shyh-Fann Ting, Wei Chuang Wu, Yen-Ting Chiang, Chia Ching Liao, Yen-Yu Chen
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Patent number: 11948938Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.Type: GrantFiled: July 18, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
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Patent number: 9773534Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.Type: GrantFiled: May 19, 2016Date of Patent: September 26, 2017Assignee: Faraday Technology Corp.Inventors: Kun-Chih Chen, Hsiao-An Chuang
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Publication number: 20170221535Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.Type: ApplicationFiled: May 19, 2016Publication date: August 3, 2017Inventors: Kun-Chih Chen, Hsiao-An Chuang
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Patent number: 8892278Abstract: A method for implementing an overhead rail guided transport system includes the following steps: a vehicle transport system is provided, which includes an upper rail guided transport system, a lower rail guided transport system, a vehicle exchange equipment, and a plurality of vehicles operating in the upper and lower rail guided transport system; respective vehicle utilizing rates in the upper and lower rail guided transport systems are provided; the vehicle exchange equipment is used to interchange the vehicles respectively operating in the upper and lower rail guided transport systems in order to equilibrate the respective vehicle utilizing rates.Type: GrantFiled: March 15, 2012Date of Patent: November 18, 2014Assignee: Inotera Memories, Inc.Inventors: Huan-Cheng Lin, Chin-Hsiao Chuang
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Patent number: 8655483Abstract: A wafer cassette transportation method includes the steps: (a) Provide a monitoring system, overhead platforms, a detection system, and a plurality of transportation systems; (b) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits first signals to the monitoring system; (c) The monitoring system reads the first signals and instructs one of the transportation systems to move the wafer cassette to an empty overhead platform; (d) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits second signals to the monitoring system; and (e) The monitoring system reads the second signals and instructs another transportation system to move the wafer cassette away from the overhead platform, so as to enhance the transportation speed of the wafer cassette and lower the manufacturing cost. The present invention further provides a wafer cassette transportation system.Type: GrantFiled: October 1, 2008Date of Patent: February 18, 2014Assignee: Inotera Memories, Inc.Inventors: Chin-Hsiao Chuang, Yu-Kun Chen
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Publication number: 20130138277Abstract: A method for implementing an overhead rail guided transport system includes the following steps: a vehicle transport system is provided, which includes an upper rail guided transport system, a lower rail guided transport system, a vehicle exchange equipment, and a plurality of vehicles operating in the upper and lower rail guided transport system; respective vehicle utilizing rates in the upper and lower rail guided transport systems are provided; the vehicle exchange equipment is used to interchange the vehicles respectively operating in the upper and lower rail guided transport systems in order to equilibrate the respective vehicle utilizing rates.Type: ApplicationFiled: March 15, 2012Publication date: May 30, 2013Inventors: Huan-Cheng Lin, Chin-Hsiao Chuang
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Patent number: 8090490Abstract: An automatic recovery and transport system includes a manufacture execution system, a path planning system electrically connected with the manufacture execution system, a vehicle control system electrically connected with the path planning system, a plurality of vehicles electrically connected with the vehicle control system; and an alarm system electrically connected with the path planning system and the vehicle control system. The alarm system will command the path planning system to command the vehicle control system to drive the vehicle about to stop to enter the maintenance area immediately. Accordingly, the stability and the work efficiency of the whole system are improved. The present invention also provides a method for executing an automatic recovery and transport system.Type: GrantFiled: February 23, 2009Date of Patent: January 3, 2012Assignee: Inotera Memories, Inc.Inventors: Yu-Kun Chen, Chin-Hsiao Chuang
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Publication number: 20100087968Abstract: An automatic recovery and transport system includes a manufacture execution system, a path planning system electrically connected with the manufacture execution system, a vehicle control system electrically connected with the path planning system, a plurality of vehicles electrically connected with the vehicle control system; and an alarm system electrically connected with the path planning system and the vehicle control system. The alarm system will command the path planning system to command the vehicle control system to drive the vehicle about to stop to enter the maintenance area immediately. Accordingly, the stability and the work efficiency of the whole system are improved. The present invention also provides a method for executing an automatic recovery and transport system.Type: ApplicationFiled: February 23, 2009Publication date: April 8, 2010Applicant: INOTERA MEMORIES, INC.Inventors: YU-KUN CHEN, CHIN-HSIAO CHUANG
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Publication number: 20100023158Abstract: A wafer cassette transportation method includes the steps: (a) Provide a monitoring system, overhead platforms, a detection system, and a plurality of transportation systems; (b) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits first signals to the monitoring system; (c) The monitoring system reads the first signals and instructs one of the transportation systems to move the wafer cassette to an empty overhead platform; (d) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits second signals to the monitoring system; and (e) The monitoring system reads the second signals and instructs another transportation system to move the wafer cassette away from the overhead platform, so as to enhance the transportation speed of the wafer cassette and lower the manufacturing cost. The present invention further provides a wafer cassette transportation system.Type: ApplicationFiled: October 1, 2008Publication date: January 28, 2010Applicant: INOTERA MEMORIES, INC.Inventors: CHIN-HSIAO CHUANG, YU-KUN CHEN
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Publication number: 20100023160Abstract: A cross-fab control system and a method for using the said system are disclosed. The said system comprises a first transport system, a second transport system, a cross-area control system, and a stocker. The first transport system connects the cross-area control system. The stocker connects the second transport system and the cross-area control system. The cross-area control system is utilized to identify Front Opening Unified Pod (FOUP) data on the stocker. By the assistance of the cross-area control system, the first transport system will transport the FOUP to destination through optimize path and avoid FOUP staying on the stocker with no transport command.Type: ApplicationFiled: November 3, 2008Publication date: January 28, 2010Applicant: INOTERA MEMORIES, INC.Inventors: YU-KUN CHEN, CHIN-HSIAO CHUANG
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Publication number: 20050178760Abstract: A method of making a microneedle array structure (20) comprising a plurality of simultaneously formed microneedles (24), each microneedle (24) having a protrusion (32) and a passageway (34) extending therethrough. The method comprises the steps of pressing an embossable sheet material between a complimentary tools and radiantly heating the sheet material using radiant energy from a radiant energy source. One tool is relatively-radiantly-transparent, and another tool and/or the sheet material is relatively-radiantly-absorptive.Type: ApplicationFiled: February 3, 2005Publication date: August 18, 2005Inventors: Eng-Pi Chang, Philip Chu, Hsiao Chuang, Kejian Huang, Michael Lang, Reza Mehrabi, Ronald Sieloff, Karen Spilizewski, Mark Wisniewski
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Publication number: 20050167863Abstract: A method of embossing a sheet material includes: heating at least a portion of the sheet directly or indirectly with radiant energy from a radiant energy source; pressing a tool against the heated portion of the sheet, thereby patterning a surface of the sheet; and separating the sheet and the tool. The radiant energy may travel through a solid material that is relatively transparent to radiation, on its way to being absorbed by a relatively-absorptive material. The relatively-transparent material may be an unheated portion of the sheet, and the relatively-absorptive material may be either the tool or the heated portion of the sheet. Alternatively, the relatively-transparent material may be the tool, and the relatively-absorptive material may be all or part of the sheet. The method may be performed as one or more roll-to-roll operations.Type: ApplicationFiled: January 31, 2005Publication date: August 4, 2005Inventors: Rishikesh Bharadwai, Eng-Pi Chang, Philip Chu, Hsiao Chuang, David Edwards, Robert Fermin, Ali Mehrabi, Reza Mehrabi, Ronald Sieloff, Chunhwa Wang