Abstract: A photonic integrated circuit structure includes a substrate, a waveguide structure and a spot size converter. The waveguide structure is disposed over a surface of the substrate and has a receiving end. The spot size converter includes a concave mirror and a curved mirror. The concave mirror and the curved mirror are opposite to each other and have a common focus. The concave mirror is arranged to reflect a parallel beam from a transmitting end such that a first reflected beam is able to converge at the common focus, and the curved mirror is arranged to reflect the first reflected beam such that a second reflected beam is directed parallel to the receiving end of the waveguide structure.

Abstract: A photonic integrated circuit structure includes a substrate, a waveguide structure and a spot size converter. The waveguide structure is disposed over a surface of the substrate and has a receiving end. The spot size converter includes a concave mirror and a curved mirror. The concave mirror and the curved mirror are opposite to each other and have a common focus. The concave mirror is arranged to reflect a parallel beam from a transmitting end such that a first reflected beam is able to converge at the common focus, and the curved mirror is arranged to reflect the first reflected beam such that a second reflected beam is directed parallel to the receiving end of the waveguide structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: The present disclosure provides an image sensor, a color filter array, and a preparation method thereof. The method includes: etching a photosensitive array substrate to form a plurality of strip-shaped first color filters, arranged at intervals in a first direction, a width direction thereof being parallel to the first direction; and etching the photosensitive array substrate to form block-shaped second and third color filters, the second and third color filters being disposed within the intervals of the first color filters and distributed in a second direction alternately, wherein the first direction is perpendicular to the second direction. An RGB arrangement manner different from a traditional manner is proposed from the perspective of layout design, thereby breaking a single RGB layout arrangement manner and providing more space for RGB design.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract: An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber.

Abstract: A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d? to cover and completely seal the surface of the oxide layer, wherein d?<d1 and d1+d??1/2D; forming an insulating layer to fill the trench; and conducting a planarization process wherein the patterned mask is used as a stop layer. In the semiconductor substrate, the oxide layer, essentially composed of the flowable oxide, is confined in an isolated region.

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract: A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.

Abstract: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

Abstract: An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

Abstract: A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

Abstract: A method for improving atomic layer deposition (ALD) performance and an apparatus thereof are disclosed. The apparatus alternates the process temperature of the different ALD steps rapidly, and the process temperature of each step is determined in accordance with the specific precursor and the substrate surface used. In case a higher process temperature is needed, a plurality of heating units of the apparatus increases and keeps the temperature of the deposited substrate to complete surface reaction. When the lower process temperature is needful for the next ALD step, the heating units are turned off to reduce the temperature of the deposited substrate and a gas flow puffed to the heater and the deposited substrate to assist in temperature cooling.