Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: Embodiments relate to a neural processor circuit that includes a first number of neural engine circuits, a second number of channels and a data processor circuit. The first number of neural engine circuits are pipelined into the second number of chains smaller than the first number. Each of the chains is configured to generate output data of a first size. Each of the channels is coupled to each of the chains and configured to transmit the output data from each of the neural engine circuits in the chains sequentially. The data processor circuit is coupled to the channels to receive the output data. The data processor circuit aggregates the output data of each of the chains into aggregated data of a second size larger than the first size and writes the aggregated data of the second size into a buffer memory of the data processor circuit.

Abstract: The vibration damping system includes a vibration damping device on a processing machine and a control unit. The vibration damping device includes a base, a rigid module, a drive module, a counterweight module and a damping module disposed on the counterweight module. The rigid module includes a holder, a guide bar connected to the holder and a moving member disposed on the guide bar. The drive module drives the moving member to move along a first axis. The counterweight module includes a guider and a counterweight mass unit movable along a second axis through the guider. The control unit controls the processing machine and controls the drive module to change a position of the moving member along the first axis according to a vibration frequency of the processing machine in real time, so that vibration frequencies of the vibration damping device and the processing machine are matched.

Abstract: A method for identifying inner and outer tire pressure sensors, which includes the following steps: Signal Reception Step, Signal Strength Summation Step, and Inner and Outer Wheel Identification Step. The vehicle main unit receiving the first inner wheel detection signal strength total value and the first outer wheel detection signal strength total value, and compares their magnitudes. The larger value indicates the inner wheel, while the smaller value indicates the outer wheel. The vehicle main unit identifies inner and outer wheels by having tire pressure sensors read and recognize the signal strength of tire pressure sensors in mirror-image positions. Compared to traditional methods, this approach can more accurately identify tire pressure sensors on inner and outer wheels.

Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. A first portion of the cover structure extends between the first and second dummy gate stacks. The method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. The first and second epitaxial features merge after rising above a top surface of the fins.

Abstract: A semiconductor structure a method of fabricating thereof including a substrate having a device region and a dummy region. A first active region is disposed over the substrate in the device region and a second active region is over the substrate in the dummy region. A first operational gate structure over the first active region and a first non-operational gate structure over the second active region. A first epitaxial region of an n-type dopant is adjacent the first operation gate structure; and a second epitaxial region of an n-type dopant is adjacent the first non-operational gate structure.

Abstract: Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.

Abstract: A semiconductor structure includes a first circuit area having first fin active regions extending lengthwise along a first direction, each of the first fin active regions includes first channel regions; a second circuit area having second fin active regions extending lengthwise along the first direction, each of the second fin active regions includes second channel regions; a gate connector area between and separating the first and the second circuit areas, the gate connector area having filter fins extending lengthwise along the first direction; and a gate structure extending across the first circuit area, the gate connector area, and the second circuit area along a second direction over the first and second channel regions and the filter fins. A portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. The gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. The two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. The two gate electrodes have a first width (W0) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to W0 (W/W0) is at least 1.1.

Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.

Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; determining a bias voltage of an electron beam writer system, the bias voltage applicable to an inspection operation and a repairing operation; and performing the repairing operation on the photomask by the electron beam writer system with the bias voltage.

Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; receiving information of the photomask; determining a bias voltage of an electron beam writer system according to the information; and performing a repairing operation on the photomask by the electron beam writer system with the bias voltage.

Abstract: Embodiments of the present disclosure set forth a method to determine an operation pathway for a patient. The method includes constructing a three-dimensional model of the patient; obtaining image information of the patient; selecting a first set of two-dimensional feature points associated with the three-dimensional model and a second set of two-dimensional feature points associated with the image information; transforming the first set of two-dimensional feature points to a first set of three-dimensional feature points and the second set of two-dimensional feature points to a second set of three-dimensional feature points, respectively; matching between the first set of three-dimensional feature points and the second set of three-dimensional feature points to determine a relationship that aligns the first set of three-dimensional feature points and the second set of three-dimensional feature points; and determining the operation pathway in a coordinate system associated with a robotic arm.

Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.

Abstract: Embodiments of the present invention set forth a method to update an operation pathway for a robotic arm assembly in response to a movement of a patient. The method includes processing a two-dimensional image associated with a tag having a spatial relationship with the patient. A corresponding movement of the tag in response to the movement of the patient is determined based on the spatial relationship. The tag includes a first point and a second point and the two-dimensional image includes a first point image and a second point image. The method also includes associating the first point image with the first point and the second point image with the second point and updating the operation pathway based on a conversion matrix of the first point and the second point, and the first point image and the second point image.

Abstract: A power converter includes a voltage control unit, a current control unit and a hysteresis control unit. The voltage control unit generates a first current command. The hysteresis control unit couples the voltage control unit with the current control unit and is configured to: in the first mode, decouple the voltage control unit and the current control unit and generate a second current command to be transmitted to the current control unit when the detection current reaches the first threshold value, and couple the voltage control unit with the current control unit and transmit the first current command generated by the voltage control unit to the current control unit when the first current command reaches a second threshold value for switching to a second mode from the first mode. The current control unit outputs a mode control signal according to the first current command and the second current command.

Abstract: A fatigue data generation method, comprising: obtaining, by the camera device, a target image; obtaining, by a processor, a target feature data from the target image, and inputting the target feature data to a fatigue analysis model which stored in a storage unit, wherein the fatigue analysis model comprises a plurality of reference physiological signals, a plurality of reference feature data, a plurality of reference fatigue data and a plurality of correlation parameters; and generating a target fatigue data according to the target feature data, the plurality of reference feature data and the plurality of correlation parameters.