Patents by Inventor Hsiao Chen

Hsiao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289900
    Abstract: A high electron mobility transistor includes a substrate. A channel layer is disposed on the substrate. An active layer is disposed on the channel layer. The active layer includes a P-type aluminum gallium nitride layer. A P-type gallium nitride gate is disposed on the active layer. A source electrode and a drain electrode are disposed on the active layer.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: April 29, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee, Wei-Jen Chen
  • Patent number: 12266723
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Grant
    Filed: March 6, 2024
    Date of Patent: April 1, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Publication number: 20250098254
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according to one embodiment includes forming a plurality of fins protruding from a substrate, forming first and second dummy gate stacks over the fins, and depositing a cover structure over the fins. A first portion of the cover structure extends between the first and second dummy gate stacks. The method also includes etching the fins to form a first trench between the first dummy gate stack and the first portion of the cover structure and a second trench between the second dummy gate stack and the first portion of the cover structure, removing the cover structure, epitaxially growing a first epitaxial feature from the first trench and a second epitaxial feature from the second trench. The first and second epitaxial features merge after rising above a top surface of the fins.
    Type: Application
    Filed: January 25, 2024
    Publication date: March 20, 2025
    Inventors: Hou-Hsueh Wu, Wei Hsin Lin, Hui-Hsuan Kung, Yi-Lii Huang, Chih-Hsiao Chen
  • Publication number: 20250081623
    Abstract: A semiconductor structure a method of fabricating thereof including a substrate having a device region and a dummy region. A first active region is disposed over the substrate in the device region and a second active region is over the substrate in the dummy region. A first operational gate structure over the first active region and a first non-operational gate structure over the second active region. A first epitaxial region of an n-type dopant is adjacent the first operation gate structure; and a second epitaxial region of an n-type dopant is adjacent the first non-operational gate structure.
    Type: Application
    Filed: February 1, 2024
    Publication date: March 6, 2025
    Inventors: Yi-Hui Chen, Yi-Lii Huang, Chih-Hsiao Chen, Ming Chen Hung, Yen Wei Tseng, Yi-Chen Li
  • Publication number: 20250072038
    Abstract: Embodiments of the present disclosure provide a FinFET semiconductor including a first set of fin structures that are active, a source/drain (S/D) region in contact with the first set of fin structures, a second set of fin structures separated, via a shallow trench isolation (STI) feature, from the first set of fin structures, a contact etch stop layer (CESL) over the S/D region and over the second set of fin structures, and a gate over the first set of fin structures and over the second set of fin structures, the gate including a gate dielectric and a gate electrode over the gate dielectric. The second set of fin structures includes one or more non-active fin structures that are in contact with the CESL without being in contact with the S/D region.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 27, 2025
    Inventors: Yi Hong Wang, Hui-Hsuan Kung, Yi-Lii Huang, Chih-Hsiao Chen
  • Publication number: 20250072039
    Abstract: A semiconductor structure includes a first circuit area having first fin active regions extending lengthwise along a first direction, each of the first fin active regions includes first channel regions; a second circuit area having second fin active regions extending lengthwise along the first direction, each of the second fin active regions includes second channel regions; a gate connector area between and separating the first and the second circuit areas, the gate connector area having filter fins extending lengthwise along the first direction; and a gate structure extending across the first circuit area, the gate connector area, and the second circuit area along a second direction over the first and second channel regions and the filter fins. A portion of the gate structure in the gate connector area has a greater resistivity than portions of the gate structure in the first and the second circuit areas.
    Type: Application
    Filed: January 24, 2024
    Publication date: February 27, 2025
    Inventors: Yi-Hong Wang, Hui-Hsuan Kung, Tien Yu Chu, Chih-Hsiao Chen, Yi-Chen Li
  • Publication number: 20250015127
    Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes: a substrate, a first circuit region and a second circuit region extending in a first direction, and a gate structure extending in a second direction that is substantially perpendicular to the first direction. The gate structure further includes: two gate electrode sections respectively located in the first and second circuit regions, and a low-resistance section between and interconnecting the two gate electrode sections. The two gate electrode sections are configured as gate electrodes for two transistors respectively located in the first and second circuit regions. The two gate electrodes have a first width (W0) along the first direction, the low-resistance section has a second width (W) along the first direction, and a ratio of W to W0 (W/W0) is at least 1.1.
    Type: Application
    Filed: July 3, 2023
    Publication date: January 9, 2025
    Inventors: Tien Yu Chu, Yi-Li Huang, Hui-Hsuan Kung, Chih-Hsiao Chen
  • Patent number: 12176403
    Abstract: A high electron mobility transistor (HEMT) device including the following components is provided. A gate electrode is located on a barrier layer. A source electrode is located on the first side of the gate electrode. A drain electrode is located on the second side of the gate. A source field plate is connected to the source electrode. The source field plate includes first, second, and third field plate portions. The first field plate portion is connected to the source electrode and is located on the first side of the gate electrode. The second field plate portion is located on the second side of the gate electrode. The third field plate portion is connected to the end of the first field plate portion and the end of the second field plate portion. The source field plate has a first opening located directly above the gate electrode.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: December 24, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Hsiao Chen, Tzyy-Ming Cheng, Wei Jen Chen, Kai Lin Lee
  • Publication number: 20240377721
    Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; determining a bias voltage of an electron beam writer system, the bias voltage applicable to an inspection operation and a repairing operation; and performing the repairing operation on the photomask by the electron beam writer system with the bias voltage.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: HAO-MING CHANG, CHING-CHIH CHUANG, HSIAO-CHEN LI
  • Patent number: 12140858
    Abstract: A method includes: providing a photomask used in extreme ultra violet (EUV) lithography; receiving information of the photomask; determining a bias voltage of an electron beam writer system according to the information; and performing a repairing operation on the photomask by the electron beam writer system with the bias voltage.
    Type: Grant
    Filed: July 30, 2023
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hao-Ming Chang, Ching-Chih Chuang, Hsiao-Chen Li
  • Patent number: 12096988
    Abstract: Embodiments of the present disclosure set forth a method to determine an operation pathway for a patient. The method includes constructing a three-dimensional model of the patient; obtaining image information of the patient; selecting a first set of two-dimensional feature points associated with the three-dimensional model and a second set of two-dimensional feature points associated with the image information; transforming the first set of two-dimensional feature points to a first set of three-dimensional feature points and the second set of two-dimensional feature points to a second set of three-dimensional feature points, respectively; matching between the first set of three-dimensional feature points and the second set of three-dimensional feature points to determine a relationship that aligns the first set of three-dimensional feature points and the second set of three-dimensional feature points; and determining the operation pathway in a coordinate system associated with a robotic arm.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: September 24, 2024
    Assignee: BRAIN NAVI BIOTECHNOLOGY CO., LTD.
    Inventors: Chieh Hsiao Chen, Kuan Ju Wang
  • Publication number: 20240213361
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Application
    Filed: March 6, 2024
    Publication date: June 27, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Patent number: 11998279
    Abstract: Embodiments of the present invention set forth a method to update an operation pathway for a robotic arm assembly in response to a movement of a patient. The method includes processing a two-dimensional image associated with a tag having a spatial relationship with the patient. A corresponding movement of the tag in response to the movement of the patient is determined based on the spatial relationship. The tag includes a first point and a second point and the two-dimensional image includes a first point image and a second point image. The method also includes associating the first point image with the first point and the second point image with the second point and updating the operation pathway based on a conversion matrix of the first point and the second point, and the first point image and the second point image.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: June 4, 2024
    Assignee: Brain Navi Biotechnology Co., Ltd.
    Inventors: Chieh Hsiao Chen, Kuan Ju Wang
  • Patent number: 11998541
    Abstract: Disclosed herein is a method for alleviating a chronic liver disease, comprising administrating to a subject in need thereof a pharmaceutical composition containing rosoxacin.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: June 4, 2024
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Jinn-Moon Yang, Shey-Cherng Tzou, Ming-Lung Yu, Yun-Ti Chen, Hsiao-Chen Huang, Jung-Yu Lee
  • Patent number: 11990837
    Abstract: A power converter includes a voltage control unit, a current control unit and a hysteresis control unit. The voltage control unit generates a first current command. The hysteresis control unit couples the voltage control unit with the current control unit and is configured to: in the first mode, decouple the voltage control unit and the current control unit and generate a second current command to be transmitted to the current control unit when the detection current reaches the first threshold value, and couple the voltage control unit with the current control unit and transmit the first current command generated by the voltage control unit to the current control unit when the first current command reaches a second threshold value for switching to a second mode from the first mode. The current control unit outputs a mode control signal according to the first current command and the second current command.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 21, 2024
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventor: Jing-Hsiao Chen
  • Publication number: 20240127944
    Abstract: A fatigue data generation method, comprising: obtaining, by the camera device, a target image; obtaining, by a processor, a target feature data from the target image, and inputting the target feature data to a fatigue analysis model which stored in a storage unit, wherein the fatigue analysis model comprises a plurality of reference physiological signals, a plurality of reference feature data, a plurality of reference fatigue data and a plurality of correlation parameters; and generating a target fatigue data according to the target feature data, the plurality of reference feature data and the plurality of correlation parameters.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 18, 2024
    Inventors: Wen-Chien HUANG, Hong-En CHEN, Hsiao-Chen CHANG, Jing-Ming CHIU
  • Publication number: 20240119603
    Abstract: The present disclosure provides a ball tracking system and method. The ball tracking system includes camera device and processing device. The camera device is configured to generate a plurality of video frame data, wherein the video frame data includes image of ball. The processing device is electrically coupled to the camera device and is configured to: recognize the image of the ball from the plurality of video frame data to obtain 2D estimation coordinate of the ball at first frame time and utilize 2D to 3D matrix to convert the 2D estimation coordinate into first 3D estimation coordinate; utilize model to calculate second 3D estimation coordinate of the ball at the first frame time; and calibrate according to the first 3D estimation coordinate and the second 3D estimation coordinate to generate 3D calibration coordinate of the ball at the first frame time.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 11, 2024
    Inventors: Rong-Sheng WANG, Shih-Chun CHOU, Hsiao-Chen CHANG
  • Patent number: 11955541
    Abstract: A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chi-Hsiao Chen, Kai-Lin Lee
  • Publication number: 20240108201
    Abstract: A holding system for an endoscope includes: a sleeve device; a first movement device connected to the sleeve device; a second movement device in contact with the first movement device; and a holding device connected to the second movement device. The holding device allows the first movement device and the second movement device to be in a relatively movable state or a holding state. When the first movement device and the second movement device are in the relatively movable state, the first movement device is movable relative to the second movement device. When the first movement device and the second movement device are in the holding state, the first movement device and the second movement device hold each other.
    Type: Application
    Filed: September 27, 2023
    Publication date: April 4, 2024
    Inventor: Chieh-Hsiao Chen
  • Publication number: 20240054641
    Abstract: A jaundice analysis system includes a database and a processing device for accessing the database. The processing device includes: a data processing module for generating a training data according to an image data, correlating the training data with a category data, and storing the training data in the database; and a deep learning module for training a target convolutional neural network module with the training data correlating with the category data to obtain a trained convolutional neural network module. The image data includes a first sclera image. The trained convolutional neural network module of the processing device generates a testing data according to an input image data. The input image data includes a second sclera image of a target subject. The testing data indicates the target subject's bilirubin concentration range.
    Type: Application
    Filed: December 18, 2020
    Publication date: February 15, 2024
    Inventors: Chieh-Hsiao Chen, Yu-Hsuan Chen